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MC68HC05L25
Data Sheet
M68HC05 Microcontrollers
MC68HC05L25 Rev. 3.1 9/2005
freescale.com
Blank
MC68HC05L25
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date May, 2002 September, 2005 Revision Level 3.0 3.1 Description Reformatted to add additional page references and correct World Wide Web address Updated to meet Freescale identity guidelines. Page Number(s) N/A Throughout
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. (c) Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 3
Revision History
MC68HC05L25 Data Sheet, Rev. 3.1 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Chapter 4 Central Processor Unit (CPU) Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 7 Input/Output Ports (I/O). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 8 Oscillators and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Chapter 9 Time Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Chapter 10 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Chapter 11 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Chapter 12 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 13 Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 14 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 15 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Chapter 16 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Chapter 17 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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List of Chapters
MC68HC05L25 Data Sheet, Rev. 3.1 6 Freescale Semiconductor
Table of Contents
Chapter 1 General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4.1 Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5 XOSC1 and XOSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5.3 XOSC Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.6 PA0-PA2/KWI0-KWI2, PA3/KWI3/BZ, PA4/AD0/EVI, PA5/ADI, PA6/RMO, and PA7 . . . . 1.5.7 PB0-PB7/FP24-FP17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.8 PC0/SCK, PC1/SDO, PC2/SDI, and PC3/IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.9 BP3/FP0, FP1-FP18, and PB0-PB7/FP24-FP17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.10 BP0-BP2 and BP3/FP0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 16 20 20 20 20 21 21 21 21 22 22 22 22 22 22 22
Chapter 2 Memory Map
2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read/Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write-Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 24 24 24 24 25 25 25 25
Chapter 3 Operating Modes
3.1 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Table of Contents
3.3 3.3.1 3.3.2 3.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31 31 31 33
Chapter 4 Central Processor Unit (CPU) Core
4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 36 36 36 36
Chapter 5 Resets
5.1 5.2 5.3 5.3.1 5.3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Delay (POD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Computer Operating Properly Reset (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 40 40
Chapter 6 Interrupts
6.1 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.7 6.8 6.9 6.10 6.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Trigger Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface Interrupt (SPII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter Interrupt (EVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Interrupt (TBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ/KWI Software Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 42 42 42 42 44 45 46 46 46 46 46
Chapter 7 Input/Output Ports (I/O)
7.1 7.2 7.2.1 7.2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.2.3 7.2.4 7.2.5 7.2.6 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8
Port A Pullup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Wired-OR Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wakeup Interrupt (KWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Pullup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Wire-ORed Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Pullup Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Wired-OR Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins with Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistor Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open Drain Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54 54 54 56 61 62 62 62 62 63 64 68 68 68 68 68 71 71 71 71 72 72 73 73 74
Chapter 8 Oscillators and Clock
8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.8 8.9 8.10 8.11 8.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC Clock Divider and POR Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC and XOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC On Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC On Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC with FOSCE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC with FOSCE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC with FOSCE = 0 and STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused XOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC Clock Divider and POD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 75 76 76 76 77 77 77 77 78 78 78 80 80 80
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Chapter 9 Time Base
9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.4 9.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Submodules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Control Carrier Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buzzer Tone Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 83 83 84 85 87 88 89 90
Chapter 10 Serial Peripheral Interface
10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Out (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data In (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop/Wait Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 91 91 91 91 91 92 92 92 92 93 93 93 94 94 95 96 96 97 97 97
Chapter 11 LCD Driver
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.3.1 LCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.3.2 Fast Change Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.3.3 LCD Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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11.4 11.4.1 11.4.2 11.4.3 11.5 11.6 11.6.1 11.6.2 11.7
Terminal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLCD Bias Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Backplane Drivers (BP0-BP3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frontplane Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Connection and LCD Driver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Waveform Base Clock and LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Base Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Cycle Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified LCD Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102 102 103 103 107 110 110 110 111
Chapter 12 Analog Subsystem
12.1 12.2 12.3 12.3.1 12.3.2 12.4 12.5 12.5.1 12.5.2 12.5.3 12.6 12.7 12.8 12.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Subsystem Operation during Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Subsystem Operation during Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Conversion Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 113 113 113 113 113 113 114 114 114 114 114 115 116
Chapter 13 Event Counter
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter Timing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Counter Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 118 119 121 121 121 122
Chapter 14 Instruction Set
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 123 123 123
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14.2.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124 124 124 124 124 125 125 126 127 128 128 129 134
Chapter 15 Electrical Specifications
15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics (VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD DC Electrical Characteristics (VDD = 3.0 V, VLCD = 0 V) . . . . . . . . . . . . . . . . . . . . . . . . . LCD DC Electrical Characteristics (VDD = 5.0 V, VLCD = 2.0 V) . . . . . . . . . . . . . . . . . . . . . . . A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing (VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 137 138 138 138 139 140 141 141 142 143 143
Chapter 16 Mechanical Specifications Chapter 17 Ordering Information
17.1 17.2 17.3 17.4 17.5 17.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Ordering Forms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Program Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 147 148 148 149
MC68HC05L25 Data Sheet, Rev. 3.1 12 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC05L25 is a member of M68HC05 Family of low-cost microcontroller units (MCUs). A functional block diagram of the MC68HC05L25 is shown in Figure 1-1.
1.2 Features
* * * * * * * * * * * * * Low-Cost, HC05 Core 48-Pin Quad Flat Pack (VQFP) and 52-Pin Quad Flat Pack (TQFP) 6160 Bytes of User ROM, Including 16 Bytes of User Vectors 176 Bytes of User RAM 24 x 4 or 25 x 3 Multiplexed Liquid Crystal Display (LCD) Driver Serial Peripheral Interface (SPI) Two-Channel Analog-to-Digital (A/D) Converter 16-Bit Event Counter Time Base Timer Computer Operating Properly (COP) Watchdog Timer Infrared (IR) Remote Carrier Output (Software Selectable 33-to-67 Percent or 50-to-50 Percent Duty) Buzzer Output (Software-Selectable Frequencies) 20 Bidirectional Input/Output (I/O) Lines, Including: - Four Key Wakeup Input Lines - Software-Programmable Pullups - Software-Programmable Open-Drain Lines - High-Current (20 mA) Lines Software-Selectable Sensitivity on IRQ Interrupt (Edge- and Level-Sensitive or Edge-Sensitive Only) STOP Instruction Disable Option On-Chip Dual 4-MHz/32-kHz (Typical) Oscillator Circuits Single-Chip, Self-Check, and Test Modes Power-Saving Stop and Wait Modes
* * * * *
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 13
General Description
1.3 Mask Options
Table 1-1 shows the mask programmable options available on the MC68HC05L25. Table 1-1. Mask Option Selection
Name Selection RESET pin pullup resistor RSTR RE RD RESET pullup resistor enable (connected) RESET pullup resistor disable (not connected) OSC feedback resistor OSCR OE OD OSC feedback resistor enable (connected) OSC feedback resistor disable (not connected) XOSC feedback/ damping resistor XOSCR XE XD XOSC feedback and damping resistor enable (both connected) XOSC feedback and damping resistor disable (both not connected) STOP instruction STOPE SE SD STOP instruction enable (STOP instruction operates normally) STOP instruction disable (executing STOP will not halt OSC clock) Description
1.4 MCU Structure
The overall block diagram of the MC68HC05L25 is shown in Figure 1-1.
MC68HC05L25 Data Sheet, Rev. 3.1 14 Freescale Semiconductor
MCU Structure
OSC1 OSC2
KEY WAKEUP
OSCILLATOR SEL /2 INTERNAL PROCESSOR CLOCK TIME BASE SYSTEM (RMO/BZ)
PA0/KWI0 DATA DIRECTION REGISTER PA1/KWI1 PA2/KWI2 PORT A PA3/KWI3/BZ PA4/AD0/EVI PA5/AD1 PA6/RMO PA7
XOSC1 XOSC2
OSCILLATOR
COP SYSTEM
ADC EVI
PORT C
CPU CONTROL M68HC05 CPU CPU REGISTERS
ALU SPI
DATA DIR REG
RESET
PC0/SCK PC1/SDO PC2/SDI PC3/IRQ
ACCUMULATOR INDEX REGISTER DATA DIRCTION REGISTER STACK POINTER PB0/FP24 PB1/FP23 PB2/FP22 PORT B PB3/FP21 PB4/FP20 PB5/FP19 PB6/FP18 PB7/FP17 SRAM -- 176 BYTES 16 SELF-CHECK ROM 240 BYTES LCD DRIVERS ROM 6160 BYTES 4
PROGRAM COUNTER CONDITION CODE REG
VDD V SS
FP1-FP16 BP 0-BP3 V LCD
Figure 1-1. MC68HC05L25 Block Diagram
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 15
General Description
1.5 Functional Pin Description
NOTE A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low. Any reference to voltage, current, resistance, capacitance, time, or frequency specified in the following paragraphs will refer to the nominal values. The exact values and their tolerance or limits are specified in Chapter 15 Electrical Specifications. The MC68HC05L25 is available in the 48-pin VQFP and 52-pin TQFP. The pin assignments for the 48-pin VQFP are shown in Figure 1-2 and Table 1-2.
FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP5 FP6 FP7 FP8 FP9
48 47 46 45 44 43 42 41 40 39 38 37 FP4 FP3 FP2 FP1 BP3/FP0 BP2 BP1 BP0 VLCD OSC1 OSC2 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 PB7/FP17 PB6/FP18 PB5/FP19 PB4/FP20 PB3/FP21 PB2/FP22 PB1/FP23 PB0/FP24 PC3/IRQ PC2/SDI PC1/SDO PC0/SCK
MC68HC05L25 48-PIN VQFP
32 31 30 29 28 27 26 25
PA2/KWI2
Figure 1-2. 48-Pin VQFP Single-Chip Mode Pinout
XOSC2
MC68HC05L25 Data Sheet, Rev. 3.1 16 Freescale Semiconductor
XOSC1
VSS
RESET
PA0/KWI0
PA1/KWI1
PA3/KWI3/BZ
PA4/AD0/EVI
PA5/AD1
PA6/RMO
PA7
Functional Pin Description
Table 1-2 summarizes the 48-pin VQFP pin configurations. Table 1-2. 48-Pin VQFP Pin Configurations
Pin No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name OSC1 OSC2 VDD XOSC2 XOSC1 VSS RESET PA0/KWI0 PA1/KWI1 PA2/KWI2 PA3/KWI3/BZ PA4/AD0/EVI PA5/AD1 PA6/RMO PA7 PC0/SCK PC1/SDO PC2/SDI PC3/IRQ I/O I O DC O I DC I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 Pin Name PB0/FP24 PB1/FP23 PB2/FP22 PB3/FP21 PB4/FP20 PB5/FP19 PB6/FP18 PB7/FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 BP3/FP0 BP2 BP1 BP0 VLCD I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O DC
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 17
General Description
The pin assignments for the 52-pin TQFP are shown in Figure 1-3 and Table 1-3.
FP10 FP11 FP12 FP13 FP14 FP15 FP16 N.C. FP5 FP6 FP7 FP8 FP9
52 51 50 49 48 47 46 45 44 43 42 41 40 FP4 FP3 FP2 FP1 BP3/FP0 BP2 BP1 BP0 VLCD OSC1 OSC2 VDD N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 N.C. PB7/FP17 PB6/FP18 PB5/FP19 PB4/FP20 PB3/FP21 PB2/FP22 PB1/FP23 PB0/FP24 PC3/IRQ PC2/SDI PC1/SDO PC0/SCK
MC68HC05L25 52-PIN TQFP
34 33 32 31 30 29 28 27
PA2/KWI2
Figure 1-3. 52-Pin TQFP Single-Chip Mode Pinout
XOSC2
XOSC1
MC68HC05L25 Data Sheet, Rev. 3.1 18 Freescale Semiconductor
VSS
RESET
PA0/KWI0
PA1/KWI1
PA3/KWI3/BZ
PA4/AD0/EVI
PA5/AD1
PA6/RMO
PA7
N.C.
Functional Pin Description
Table 1-3 summarizes the 52-pin VQFP pin configurations. Table 1-3. 52-Pin TQFT Pin Configurations
Pin No. 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 Pin Name OSC1 OSC2 VDD XOSC2 XOSC1 VSS RESET PA0/KWI0 PA1/KWI1 PA2/KWI2 PA3/KWI3/BZ PA4/AD0/EVI PA5/AD1 PA6/RMO PA7 PC0/SCK PC1/SDO PC2/SDI PC3/IRQ I/O I O DC O I DC I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin No. 31 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 13 26 39 52 N.C. N.C. N.C. N.C. 6 7 8 9 Pin Name PB0/FP24 PB1/FP23 PB2/FP22 PB3/FP21 PB4/FP20 PB5/FP19 PB6/FP18 PB7/FP17 FP16 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 BP3/FP0 BP2 BP1 BP0 VLCD I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O DC
The following paragraphs describe the general function of each pin.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 19
General Description
1.5.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
1.5.2 VLCD
This pin provides an offset to the LCD driver bias for adjusting the contrast of LCD. See Chapter 11 LCD Driver for additional information.
1.5.3 RESET
This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to VDD when the power is removed. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to Chapter 5 Resets.
1.5.4 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the 2-pin on-chip oscillator. The OSC1 and OSC2 pins can accept these sets of components: 1. A crystal or ceramic resonator as shown in Figure 1-4(a) 2. An external clock signal as shown in Figure 1-4(b)
MCU MASK OPTION ROF MCU
OSC1 OSC2 4 MHz (TYPICAL)
OSC1
OSC2
UNCONNECTED CO1 CO2 EXTERNAL CLOCK (a) Crystal Connections (b) External Clock Source Connection
Figure 1-4. Oscillator Connections The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP, by default.
MC68HC05L25 Data Sheet, Rev. 3.1 20 Freescale Semiconductor
Functional Pin Description
1.5.4.1 Crystal or Ceramic Resonator The circuit in Figure 1-4(a) shows a typical 2-pin oscillator circuit for an AT-cut, parallel, resonant crystal. The crystal manufacturer's recommendations should be followed, since the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup feedback resistor of ROF between OSC1 and OSC2 can be selected as a mask option. 1.5.4.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 output not connected, as shown in Figure 1-4(b). This configuration is possible regardless of the oscillator setup.
1.5.5 XOSC1 and XOSC2
The XOSC1 and XOSC2 pins are the connections for the 2-pin on-chip oscillator. The XOSC1 and XOSC2 pins can accept these sets of components: 1. A crystal as shown in Figure 1-5(a) 2. An external clock signal as shown in Figure 1-5(b)
MCU MASK OPTION RXOF MCU RXOD XOSC1 XOSC2 XOSC1 XOSC2
32.768 kHz (TYP) UNCONNECTED CXO1 CXO2 EXTERNAL CLOCK (a) Crystal Connections (b) External Clock Source Connection
Figure 1-5. Oscillator Connections The frequency, fXOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP, if selected by SYS1:SYS0 bits. 1.5.5.1 Crystal The circuit in Figure 1-5(a) shows a typical 2-pin oscillator circuit for a 32.768-kHz "watch" crystal. The crystal manufacturer's recommendations should be followed, since the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 21
General Description
minimize output distortion. An internal startup feedback resistor of Rxof between XOSC1 and XOSC2 and a damping resistor of Rxod in series to XOSC2 can be selected as a mask option. 1.5.5.2 External Clock As shown in Figure 1-5(b), an external clock from another CMOS-compatible device can be connected to the XOSC1 input (with the XOSC2 output not connected). This configuration is possible regardless of the oscillator setup. 1.5.5.3 XOSC Not Used When XOSC is not used, the XOSC1 pin must be connected to the RESET pin to assure proper initialization of the clock circuitry. XOSC2 pin should remain unconnected.
1.5.6 PA0-PA2/KWI0-KWI2, PA3/KWI3/BZ, PA4/AD0/EVI, PA5/ADI, PA6/RMO, and PA7
Port A is an 8-bit I/O port. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. Bits 0 through 3 are shared with the key wakeup subsystem, and bit 3 also is shared with the buzzer subsystem. Bit 4 is shared with the A/D converter and event counter. Bit 5 is shared with the A/D converter. Bit 6 is shared with the infrared (IR) remote output. See Chapter 7 Input/Output Ports (I/O) for more details on the I/O ports.
1.5.7 PB0-PB7/FP24-FP17
These eight I/O lines comprise port B. The state of any pin is software programmable, and all bits are configured as LCD output during power-on or reset. These bits are shared with LCD frontplane drivers. See Chapter 7 Input/Output Ports (I/O) for more details on the I/O ports.
1.5.8 PC0/SCK, PC1/SDO, PC2/SDI, and PC3/IRQ
These four I/O lines comprise port C. Bits 0 through 2 are shared with the SPI subsystem. Bit 3 is shared with the IRQ input. The state of any pin is software programmable, and all port C lines are configured as port inputs during power-on or reset. Each port C pin can be configured with a pullup resistor by a software option. SPI output pins SCK and SDO can be configured as open-drain outputs by a software option. See Chapter 7 Input/Output Ports (I/O) for more details on the I/O ports. The PC3/IRQ pin is used for special mode entry. Do not apply voltages above VDD for normal single-chip mode operation. See Chapter 15 Electrical Specifications for more details.
1.5.9 BP3/FP0, FP1-FP18, and PB0-PB7/FP24-FP17
The LCD display has 25 frontplane drivers. Frontplanes 17 through 24 are shared with port B bits 7 through 0, respectively. Frontplane 0 is shared with backplane 3. See Chapter 11 LCD Driver for additional information.
1.5.10 BP0-BP2 and BP3/FP0
The LCD display has four backplane drivers. Backplane 3 is multiplexed with frontplane 0. See Chapter 11 LCD Driver for additional information.
MC68HC05L25 Data Sheet, Rev. 3.1 22 Freescale Semiconductor
Chapter 2 Memory Map
2.1 Introduction
When the MC68HC05L25 is in the single-chip mode, 80 bytes of input/output (I/O) registers, 176 bytes of user RAM (including a 64-byte stack), 6144 bytes of user ROM, and 16 bytes of user vectors are available in the 8-K memory map as shown in Figure 2-1.
$0000 I/O 64 BYTES $003F $0040 $004F $0050 $00BF $00C0 $00FF $0100 0063 0064 0079 0080 0000 DUAL MAPPED I/O REGISTERS 16 BYTES Figure 2-2.) $0000
$000F $0010
UNIMPLEMENTED 16 BYTES USER RAM 176 BYTES
I/O REGISTERS 48 BYTES Figure 2-2.) $003F
0191 STACK 0192 64 BYTES 0255 0256
TIME BASE VECTOR (HIGH BYTE) TIME BASE VECTOR (LOW BYTE)
$1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
UNIMPLEMENTED 1536 BYTES
SPI VECTOR (HIGH BYTE) SPI VECTOR (LOW BYTE) EVENT CNTR VECTOR (HIGH BYTE) EVENT CNTR VECTOR (LOW BYTE)
$06FF $0700
1791 1792
RESERVED RESERVED KEY WAKEUP VECTOR (HIGH BYTE)
USER ROM 6144 BYTES
KEY WAKEUP VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) IRQ VECTOR (LOW BYTE)
$1EFF $1F00 $1FEF $1FF0 $1FFF
TEST ROM AND VECTORS 240 BYTES USER VECTORS 16 BYTES
7935 7936 8175 8176 8191
SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
Figure 2-1. MC68HC05L25 Single-Chip Mode Memory Map
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 23
Memory Map
2.2 Input/Output and Control Registers
The I/O and control registers reside in locations $0000 through $003F. A summary of these registers is shown in Figure 2-3. The bit assignments for each register are shown in Figure 2-4. Reading from unimplemented bits (denoted with --) will return unknown states (unless explicitly defined to read 0), and writing to unimplemented bits will have no effect. See also Figure 2-2.
Register Address (Main map unless otherwise specified) Register Name (Full) Read
Read: Time Base Control Register 2 Write: (TBCR2) TBIF -- 0
Bit Name (Mnemonic) Read-Only Bit
TBIE 0 TBR1 1
Reserved Bit
TBR0 1 0 RTBIF 0 0 -- 0 COPE 0 0 COPC 0
$0011
Reset:
Write Register Name (Mnemonic)
Reset Value Read/Write Bit
Write-Only Bit
Figure 2-2. Register Description Key
2.2.1 Read/Write Bits
Read/write bits are typically control bits. They are, in general, not modified by a module. Reset: indicates the initial value of the latch.
2.2.2 Read-Only Bits
Read-only bits are status flag bits. They are indicators of module status. Reset: indicates the value that will be read immediately after system reset or before the module is enabled.
2.2.3 Write-Only Bits
Write-only bits are control bits. They typically return a state of 0 to prevent an inadvertent write to this bit by a READ-MODIFY-WRITE instruction. Reset: indicates the value that will be read immediately after system reset, which is the forced read value (typically 0).
2.2.4 Reserved Bits
Reserved bits are read-only bits that typically read 0. Writes to these bits are ignored, and the user should not write 1 for future compatibility. Reset: indicates the value that will be read immediately after system reset which is the forced read value of 0, typically.
MC68HC05L25 Data Sheet, Rev. 3.1 24 Freescale Semiconductor
Read-Only Memory (ROM)
2.2.5 Reset Value
Values specified on the row marked Reset: are initial values of register bits after system reset. Those bits unaffected by reset are marked with the letter U. Those bits that are unaffected by reset but initialized by power-on reset are marked with an asterisk (*).
2.2.6 Option Map
Address locations $0000 through $000F are dual mapped. When the OPTM bit in the MISC register is cleared, the main address map is accessed. When the OPTM bit in the MISC register is set, the option address map is accessed. NOTE Although not necessary for this device, the OPTM bit should be cleared when accessing memory locations $0010 and above for future compatibility.
2.2.7 Random-Access Memory (RAM)
The user RAM consists of 176 bytes (including the stack) at locations $0050 through $00FF. The stack can access 64 locations beginning at address $00FF and proceeding down to $00C0. NOTE Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
2.3 Read-Only Memory (ROM)
This chip has a total of 6160 bytes of ROM. These are implemented as 6144 bytes of user ROM at locations $0700 through $1EFF and 16 bytes of user vectors at locations $1FF0 through $1FFF. A total of 240 bytes of test ROM and vectors is located from $1F00 through $1FEF.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 25
Memory Map
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 Name (Main Map Registers) Port A Data Register Port B Data Register Port C Data Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Interrupt Control Register Interrupt Status Register Serial Peripheral Control Register Serial Peripheral Status Register Serial Peripheral Data Register Unimplemented Unimplemented Unimplemented Time Base Control Register 1 Time Base Control Register 2 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented A/D Data Register A/D Control/Status Register Time Base Control Register 3 LCD Control Register LCD Data Register 1 LCD Data Register 2 LCD Data Register 3 LCD Data Register 4 LCD Data Register 5 LCD Data Register 6 LCD Data Register 7 OPTN Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Name (Option Map Registers) Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Resistor Control Register Resistor Control Register Wired-OR Mode Register Unimplemented Unimplemented Unimplemented Key Wakeup Input Enable Register Mask Option Status Register Address $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F LCD Data Register 8 LCD Data Register 9 LCD Data Register 10 LCD Data Register 11 LCD Data Register 12 LCD Data Register 13 Event Counter Control/Status Register Event Counter Timing Register Event Counter Data High Register Event Counter Data Low Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Miscellaneous Register Unimplemented Name
Figure 2-3. I/O Register Memory Map Summary
MC68HC05L25 Data Sheet, Rev. 3.1 26 Freescale Semiconductor
Read-Only Memory (ROM)
Addr.
Register Name Port A Data Register (PORTA) See page 53. Port B Data Register (PORTB) See page 62. Port C Data Register (PORTC) See page 68. Unimplemented Unimplemented Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset:
Bit 7 PA7
6 PA6
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
Bit 0 PA0
$0000
Unaffected by reset PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$0001
Unaffected by reset 0 0 0 0 0 0 0 0 PC3 U PC2 U PC1 U PC0 U
$0002 $0003 $0007
$0008
Interrupt Control Register (INTCR) See page 44. Interrupt Status Register (INTSR) See page 45. Serial Peripheral Control Register (SPCR) See page 94. Serial Peripheral Status Register (SPSR) See page 95. Serial Peripheral Data Register (SPDR) See page 96. Unimplemented Unimplemented
IRQE 0 IRQF 0 SPIE 0 SPIF 0 SPD7
0 0 0 0 SPE 0 DCOL 0 SPD6
0 0 0 0 DORD 0 0 0 SPD5
KWIE 0 KWIF 0 MSTR 0 0 0 SPD4
IRQS 0 0 RIRQ 0 0 0 0 0 SPD3
0 0 0 0 0 0 0 0 SPD2
0 0 0 0 0 0 0 0 SPD1
0 0 0 RKWIF 0 SPR 0 0 0 SPD0
$0009
$000A
$000B
$000C $000D $000F
Unaffected by reset
$0020
LCD Control Register (LCDCR) See page 100.
Read: Write: Reset:
LCDE 0
PBEH 0
DUTY 0
PBEL 0 R
0 0 = Reserved
0 0
FC 0
LC 0
= Unimplemented
U = Unaffected
Figure 2-4. I/O Registers (Sheet 1 of 3)
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 27
Memory Map Addr. Register Name LCD Data Register (LDAT1) See page 102. LCD Data Register (LDAT2) See page 102. LCD Data Register (LDAT3) See page 102. LCD Data Register (LDAT4) See page 102. LCD Data Register (LDAT5) See page 102. LCD Data Register (LDAT6) See page 102. LCD Data Register (LDAT7) See page 102. LCD Data Register (LDAT8) See page 102. LCD Data Register (LDAT9) See page 102. LCD Data Register (LDAT10) See page 102. LCD Data Register (LDAT11) See page 102. LCD Data Register (LDAT12) See page 102. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: = Unimplemented F23B3 F23B2 F23B1 F21B3 F21B2 F21B1 F19B3 F19B2 F19B1 F17B3 F17B2 F17B1 F15B3 F15B2 F15B1 F13B3 F13B2 F13B1 F11B3 F11B2 F11B1 F9B3 F9B2 F9B1 F7B3 F7B2 F7B1 F5B3 F5B2 F5B1 F3B3 F3B2 F3B1 Bit 7 F1B3 6 F1B2 5 F1B1 4 F1B0 3 F0B3 2 F0B2 1 F0B1 Bit 0 F0B0
$0021
Unaffected by reset F3B0 F2B3 F2B2 F2B1 F2B0
$0022
Unaffected by reset F5B0 F4B3 F4B2 F4B1 F4B0
$0023
Unaffected by reset F7B0 F6B3 F6B2 F6B1 F6B0
$0024
Unaffected by reset F9B0 F8B3 F8B2 F8B1 F8B0
$0025
Unaffected by reset F11B0 F10B3 F10B2 F10B1 F10B0
$0026
Unaffected by reset F13B0 F12B3 F12B2 F12B1 F12B0
$0027
Unaffected by reset F15B0 F14B3 F14B2 F14B1 F14B0
$0028
Unaffected by reset F17B0 F16B3 F16B2 F16B1 F16B0
$0029
Unaffected by reset F19B0 F18B3 F18B2 F18B1 F18B0
$002A
Unaffected by reset F21B0 F20B3 F20B2 F20B1 F20B0
$002B
Unaffected by reset F23B0 F22B3 F22B2 F22B1 F22B0
$002C
Unaffected by reset R = Reserved U = Unaffected
Figure 2-4. I/O Registers (Sheet 2 of 3)
MC68HC05L25 Data Sheet, Rev. 3.1 28 Freescale Semiconductor
Read-Only Memory (ROM) Addr. Register Name LCD Data Register (LDAT13) See page 102. Event Control Status/Counter Register (EVSCR) See page 41. Event Counter Timing Register (EVTR) See page 119. Event Counter Data Register High (EVDH) See page 122. Event Counter Data Register Low (EVDL) See page 122. Unimplemented Unimplemented Miscellaneous Register (MISC) See page 80. Reserved Read: Write: Reset: $003F U R U R 0 R 0 R R FTUP STUP 0 0 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: 0 0 0 0 0 0 0 0 0 BIT7 0 BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 0 BIT0 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 WT3 WT2 WT1 WT0 MT3 MT2 MT1 MT0 EVCE EVIE EVOE EVIF Bit 7 0 6 0 5 0 4 0 3 F24B3 2 F24B2 1 F24B1 Bit 0 F24B0
$002D
Unaffected by reset EVOF 0 RCCF 0 ROIF 0
$002E
$002F
$0030
$0031 $0032 $003D
SYS1 0 R = Reserved
SYS0 0 R
FOSCE 1 R
OPTM 0 R
$003E
= Unimplemented
U = Unaffected
Figure 2-4. I/O Registers (Sheet 3 of 3)
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 29
Memory Map
MC68HC05L25 Data Sheet, Rev. 3.1 30 Freescale Semiconductor
Chapter 3 Operating Modes
3.1 Introduction
The MC68HC05L25 has three modes of operation that affect the pinout and architecture of the MCU: single-chip mode, internal test mode, and expanded test mode. The single-chip mode normally will be used, while the test modes are required for the special needs of production test and burn-in.
3.2 Single-Chip Mode
Single-chip mode allows the MCU to function as a self-contained microcontroller with maximum use of the pins for on-chip peripheral functions. The pinout for the single-chip mode is shown in Figure 1-2 and Figure 1-3. In single-chip mode, all address and data activity occurs within the MCU and is not available externally.
3.3 Low-Power Modes
In each of its configuration modes, the MC68HC05L25 is capable of running in one of two low-power operational modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP watchdog timer is enabled. The flow of the stop and wait modes is shown in Figure 3-1.
3.3.1 STOP Instruction
Execution of the STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing except the time base/COP watchdog timer, if it is enabled and clocked from XOSC. Execution of the STOP instruction automatically clears the I bit in the condition code register. All other registers and memory remain unaltered. All input/output lines remain unchanged. Therefore, unused ports must be programmed as output or tied to the power rails to prevent excessive current consumption. The MCU can be brought out of stop mode by an external IRQ interrupt, KWI interrupt, SPI (slave mode only) interrupt or TBI interrupt clocked by XOSC or a reset.
3.3.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode, which consumes more power than stop mode. In wait mode, the internal processor clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register and external interrupt is allowed. All other registers, memory, and input/output lines remain in their previous states.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 31
Operating Modes
STOP
WAIT EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE
STOP OSCILLATOR AND ALL CLOCKS EXCEPT XOSC AND CLEAR I BIT IN CCR.
STOP INTERNAL PROCESSOR CLOCK.
EXTERNAL RESET? N IRQ EXTERNAL INTERRUPT? N
Y
Y
EXTERNAL RESET? N
Y Y
IRQ EXTERNAL INTERRUPT? N
KWI INTERRUPT? N SPI INTERRUPT? N TBI INTERRUPT? N
Y
Y
KWI INTERRUPT? N
Y
Y
EVI INTERRUPT? N
Y
Y
SPI INTERRUPT? N
Y RESTART INTERNAL PROCESSOR CLOCK.
TBI INTERRUPT? N
NOTES: For slave mode only When clocked by XOSC
FETCH RESET VECTOR OR SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
Figure 3-1. Stop/Wait Flowcharts
MC68HC05L25 Data Sheet, Rev. 3.1 32 Freescale Semiconductor
COP Watchdog Timer Considerations
If time base interrupts are enabled, a time base interrupt will cause the processor to exit the wait mode and resume normal operation. The time base may be used to generate a periodic exit from the wait mode. The wait mode also may be exited when an external interrupt (IRQ) or reset occurs.
3.4 COP Watchdog Timer Considerations
The COP watchdog timer is active in all modes of operation if enabled by a TBCR2 select bit. If the COP watchdog timer is selected by the TBCR2 bit, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the oscillator (OSC) to halt and thus the COP watchdog timer will not time out if driven from OSC. Thus for applications that require use of COP watchdog from OSC, STOP instruction must be disabled, or COP must be driven from XOSC. If the COP watchdog timer is selected by the TBCR2 select bit, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP watchdog should be disabled for a system that must have intentional uses of the wait or stop modes for periods longer than the COP timeout period.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 33
Operating Modes
MC68HC05L25 Data Sheet, Rev. 3.1 34 Freescale Semiconductor
Chapter 4 Central Processor Unit (CPU) Core
4.1 Introduction
The MC68HC05L25 has an 8-K memory map. Therefore, it uses 13 bits of the address bus.
4.2 Registers
The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 4-1.
7 6 5 4 3 2 1 0 A
ACCUMULATOR
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0 1 1
INDEX REGISTER
X
STACK POINTER
SP
0
0
0
PROGRAM COUNTER
PC
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT
Figure 4-1. M68HC05 Programming Model
4.2.1 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 4-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is unaffected by a reset of the device.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 35
Central Processor Unit (CPU) Core
4.2.2 Index Register
The index register shown in Figure 4-1 is an 8-bit register that can perform two functions: 1. Indexed addressing 2. Temporary storage In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register contents to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register contents to a 16-bit immediate value. The index register also can serve as an auxiliary accumulator for temporary storage. The index register is unaffected by a reset of the device.
4.2.3 Stack Pointer
The stack pointer shown in Figure 4-1 is an internal 16-bit register. In devices with memory maps less than 64 Kbytes, the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the 10 most significant bits are permanently set to 0000000011. The five least significant register bits are appended to these 11 fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts CAN use up to 64 ($40) locations. If 64 locations are exceeded, the stack pointer wraps around and writes over the previously stored information. A subroutine call occupies two locations on the stack; and an interrupt uses five locations.
4.2.4 Program Counter
The program counter shown in Figure 4-1 is an internal 16-bit register. In devices with memory maps less than 64 Kbytes, the unimplemented upper address lines are ignored, and memory image is mirrored. The program counter contains the address of the next instruction or operand to be fetched. Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
4.2.5 Condition Code Register
The condition code register shown in Figure 4-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. The condition code register should be thought of as having three additional upper bits that are always 1s. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register. Half-Carry Bit (H Bit) When the H bit is set, a carry has occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
MC68HC05L25 Data Sheet, Rev. 3.1 36 Freescale Semiconductor
Registers
Interrupt Mask (I Bit) When the I bit is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can be cleared only by the clear I bit (CLI), STOP, or WAIT instructions. Negative Bit (N Bit) The N bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical 1.) The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. Zero Bit (Z Bit) The Z bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. Carry/Borrow Bit (C Bit) The C bit is set when a carry out of accumulator bit 7 occurs during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit also is set or cleared during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or DEC instruction.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 37
Central Processor Unit (CPU) Core
MC68HC05L25 Data Sheet, Rev. 3.1 38 Freescale Semiconductor
Chapter 5 Resets
5.1 Introduction
The MCU can be reset from three sources: one external input and two internal restart conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. All peripheral modules which drive external pins will be reset by the synchronous reset signal (RST) coming from a latch, which is synchronized to the PH2 bus clock and set by any of the three reset sources.
RESET OSC DATA ADDRESS
COP WATCHDOG (COPR) CPU S TO OTHER PERIPHERALS
VDD
POWER-ON DELAY (POD) PH2 IS AN INTERNAL BUS PH2
LATCH
RST
Figure 5-1. Reset Block Diagram
5.2 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU. NOTE Activation of the RST signal generally is referred to as reset of the device, unless otherwise specified.
5.3 Internal Resets
The two internally generated resets are the initial power-on delay function and the COP watchdog timer reset. Termination of the external RESET input or the internal COP watchdog timer are the only reset sources that can alter the operating mode of the MCU. The other internal resets will not have any effect on the mode of operation when their reset state ends.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 39
Resets
5.3.1 Power-On Delay (POD)
The internal POD is generated on power-up to allow the clock oscillator to stabilize. The POD is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of between 8,064 and 8,192 internal processor bus clock cycles (PH2) after the oscillator becomes active. The power-on reset (POR) will generate the RST signal which will reset the CPU. If any other reset function is active at the end of this 8,064- to 8,192-cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end.
5.3.2 Computer Operating Properly Reset (COPR)
The internal COPR reset is generated automatically (if enabled via a TBCR2 select bit) by a timeout of the COP watchdog timer. This timeout occurs if the counter in the COP watchdog timer is not reset (cleared) within a specific time by a program reset sequence. The COP watchdog timer can be disabled by a TBCR2 select bit. Refer to 9.2.4 COP for more information on this timeout feature. The COPR will generate the RST signal which will reset the CPU and other peripherals. If any other reset function is active at the end of the COPR reset signal, the RST signal will remain in the reset condition until the other reset condition(s) end.
MC68HC05L25 Data Sheet, Rev. 3.1 40 Freescale Semiconductor
Chapter 6 Interrupts
6.1 Introduction
The MCU can be interrupted in these ways: 1. Nonmaskable software interrupt instruction (SWI) 2. External interrupt via IRQ (IRQ) 3. Serial peripheral interface interrupt (SPII) 4. Internal time base interrupt (TBI) 5. Key wakeup interrupt (KWI) 6. Event counter overflow interrupt (EVOF)
6.2 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, then stacks the current CPU register states, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending after the stacking operation, the interrupt with the highest vector location shown in Table 6-1 will be serviced first. The SWI is executed in the same way as any other instruction, regardless of the I bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $1FF0 through $1FFF as defined in Table 6-1. Table 6-1. Vector Address for Interrupts and Reset
Regist er N/A N/A INTCR KWIEN -- EVSC R SPSR TBCR2 Flag Name N/A N/A IRQF KWIF -- ECOF SPIF TBIF Interrupts Reset Software External Interrupt Key Wakeup Reserved Event Counter Serial Peripheral Time Base Periodical CPU Interrupt RESET SWI IRQ KWI -- EVI SPII TBI Vector Address $1FFE:$1FFF $1FFC:$1FFD $1FFA:$1FFB $1FF8:$1FF9 $1FF6:$1FF7 $1FF4:$1FF5 $1FF2:$1FF3 $1FF0:$1FF1
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 41
Interrupts
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 6-1 shows the sequence of events that occurs during interrupt processing.
6.3 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 6-1. A low level input on the RESET pin or internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $1FFE through $1FFF. The I bit in the condition code register also is set. The MCU is configured to a known state during this type of reset as previously described in Chapter 5 Resets.
6.4 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts which were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD.
6.5 Hardware Interrupts
All hardware interrupts except reset are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Two types of hardware interrupts are explained in the following sections.
6.6 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. The IRQ pin is enabled by the IRQE bit in the INTCR. Also see 7.4 Port C. The interrupt service routine address is specified by the contents of memory locations $1FFA:$1FFB. CPU instructions BIH and BIL test the pin state of the PC3/IRQ pin.
6.6.1 External Interrupt Trigger Condition
External interrupt (IRQ) is activated by the negative-edged signal.
H PC3/IRQ L tILIH tILIL
The limit on the minimum pulse width (tILIH) is as specified. The pulse interval (tILIL) must be longer than the interrupt service routine's service time + 21 machine cycles.
MC68HC05L25 Data Sheet, Rev. 3.1 42 Freescale Semiconductor
External Interrupt (IRQ)
FROM RESET
Y
IS I BIT SET? N IRQ INTERRUPT? N IRQ INTERRUPT? N SPI INTERRUPT? N Y Y Y
TIME BASE INTERRUPT? N
Y
STACK PC, X, A, CC. SET I BIT IN CCR.
FETCH NEXT INSTRUCTION.
PC = PC+1 LOAD PC FROM: SWI: $1FFC:$1FFD IRQ: $1FFA:$1FFB KWI: $1FF8:$1FF9 EVI: $1FF4:$1FF5 SPII: $1FF2:$1FF3 TBI: $1FF0:$1FF1
SWI INSTRUCTION ? N
Y
RTI INSTRUCTION ? N EXECUTE INSTRUCTION.
Y
RESTORE REGISTERS FROM STACK CC, A, X, PC.
Figure 6-1. Interrupt Processing Flowchart
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 43
Interrupts
6.6.2 Interrupt Control Register
Address: Read: Write: Reset: $0008 Bit 7 IRQE 0 6 0 0 5 0 0 4 KWIE 0 3 IRQS 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 6-2. Interrupt Control Register (INTCR) IRQE -- External Interrupt (IRQ) Enable The IRQE bit enables external interrupt when the interrupt mask is cleared and IRQF is set. This bit is cleared at reset. 1 = IRQ enabled 0 = IRQ disabled Bits 6-5 -- Reserved These bits are not used and always return to zero. KWIE -- KWI Enable The KWIE bit enables key wakeup interrupt when the KWIF bit is set. The KWIEx bit in the KWIEN register also must be set for enabling KWI. This bit is cleared at reset. 1 = KWI enabled 0 = KWI disabled IRQS -- External Interrupt (IRQ) Select Edge Sensitivity Only The IRQS bit determines whether the LEVEL and EDGE or EDGE only will trigger the IRQ interrupt. This bit is cleared at reset. 1 = Trigger only on negative EDGEs 0 = Trigger on low LEVEL and negative EDGEs Bits 2-0 -- Reserved These bits are not used and always return to zero.
MC68HC05L25 Data Sheet, Rev. 3.1 44 Freescale Semiconductor
External Interrupt (IRQ)
6.6.3 Interrupt Status Register
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented $0009 Bit 7 IRQF 6 0 5 0 4 KWIF 3 0 RIRQF 0 0 0 2 0 1 0 Bit 0 0 RKWIF 0
Figure 6-3. Interrupt Status Register (INSTR) IRQF -- External Interrupt (IRQ) Flag A falling edge on the IRQ pin sets the IRQF bit. If the IRQE bit and this bit are set and the interrupt mask is cleared, an interrupt is generated. This is a read-only bit. Clearing IRQF is accomplished by writing a one to the RIRQF bit. Reset clears this bit. Bits 6-5 -- Reserved These bits are not used and always read zero. KWIF -- Key Wakeup Interrupt Flag When the KWIEx bit in the KWIEN register is set, the falling edge at the KWIx pin sets the KWIF bit. If the KWIE bit and this bit are set, an interrupt is generated. This bit is a read-only bit and clearing it is accomplished by writing a one to the RKWIF bit. Reset clears this bit. RIRQF -- Reset IRQ Flag The RIRQF bit is a write-only bit and always read as zero. Writing a one to this bit clears the IRQF bit and writing zero to this bit has no effect. 1 = Clear IRQF 0 = No effect Bits 2-1 -- Reserved These bits are not used and always read zero. RKWIF -- Reset KWI Flag The RKWIF bit is a write-only bit and always read as zero. Writing a one to this bit clears the KWIF bit, and writing zero to this bit has no effect. 1 = Clear KWIF 0 = No effect
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 45
Interrupts
6.7 Serial Peripheral Interface Interrupt (SPII)
The SPII is generated by the serial peripheral interface system at the end of one byte of data transmission or reception. The I bit in the CCR must be clear and the SPIE bit of SPCR must be set for the SPII to be generated. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF2 and $1FF3. See Chapter 10 Serial Peripheral Interface for more information.
6.8 Event Counter Interrupt (EVI)
The EVI interrupt is generated by the event counter system. The I bit in the CCR must be clear for the EVI interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF4 and $1FF5. See Chapter 13 Event Counter for more information.
6.9 Time Base Interrupt (TBI)
The TBI is generated periodically by the time base system. The I bit in the CCR must be clear for the TBI to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF0:$1FF1. See Chapter 9 Time Base for more information.
6.10 Key Wakeup Interrupt (KWI)
The KWI interrupt is generated by the key wakeup system. The I bit in the CCR must be clear for the KWI interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF8 and $1FF9. See Chapter 7 Input/Output Ports (I/O) for more information.
6.11 IRQ/KWI Software Consideration
IRQ and KWI interrupts have a timing delay in a case as shown in Figure 6-5. This section shows programming for proper interrupts with IRQ or KWI. Figure 6-4 shows an example of a timer interrupt. In this case, the interrupt by TOF occurs as soon as TOIE (timer overflow interrupt enable) bit is set.
. . CLI BSET TOIE, TCR LDA #$55 . . .
TOF Interrupt pending Interrupt occurs before this instruction
Figure 6-4. Timer Interrupt
MC68HC05L25 Data Sheet, Rev. 3.1 46 Freescale Semiconductor
IRQ/KWI Software Consideration
Figure 6-5 shows an example of an IRQ interrupt. In this case, the interrupt occurs after execution of the instruction which sets the IRQE bit. A similar precaution is required for KWI interrupts.
. . CLI BSET IRQE, INTCR LDA #$55 . . .
IRQ Interrupt pending Interrupt occurs after this instruction
Figure 6-5. IRQ Timing Delay
This problem can be solved by using a software code as illustrated in Figure 6-6. A similar procedure should be used for KWI.
. . CLI BSET IRQE, INTCR NOP LDA #$55 . .
IRQ Interrupt pending Interrupt occurs after this instruction
Figure 6-6. Software Patch for IRQ
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 47
Interrupts
MC68HC05L25 Data Sheet, Rev. 3.1 48 Freescale Semiconductor
Chapter 7 Input/Output Ports (I/O)
7.1 Introduction
In single-chip mode, 20 bidirectional input/output (I/O) lines are arranged as three ports: A, B, and C. Individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). If enabled by select bits in RCR or WOMR, port pins may have software programmable pullup resistors or open-drain outputs, respectively.
7.2 Port A
Port A is an 8-bit bidirectional port which shares bits 0-3 with the key wakeup subsystem, and bit 3 also is shared with the buzzer subsystem as shown in Figure 7-1 and Figure 7-2. Bit 4 is shared with the analog-to-digital (A/D) converter and the event counter subsystems as shown in Figure 7-3. Bit 5 is shared with the A/D converter subsystem as shown in Figure 7-4. Bit 6 is shared with the time base subsystem as shown in Figure 7-5. Each port A pin is controlled by the corresponding bits in a data direction register and data register enable bits of appropriate subsystems. The port A data register is located at address $0000. The port A data direction register (DDRA) is located at address $0000 of the option map. Reset clears the DDRA. The port A data register is unaffected by reset. Port A bits 0-3, when configured as an output port, is an open-drain output. Each pin can sink a maximum of 20 mA at VDD = 5.0 V and VOL (max) = 0.8 V. See Chapter 15 Electrical Specifications.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 49
Input/Output Ports (I/O)
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT*
READ $0000
KWI REGISTER BIT *NOTE: OPEN DRAIN OUTPUT INTERNAL HC05 DATA BUS RESET (RST)
Figure 7-1. Port A0:A2/KWI0:KWI2 I/O Circuitry
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
BUZZER SUBSYSTEM READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT*
READ $0000
KWI REGISTER BIT INTERNAL HC05 DATA BUS RESET (RST) *NOTE: OPEN DRAIN OUTPUT
Figure 7-2. Port A3/KWI3/BZ I/O Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 50 Freescale Semiconductor
Port A
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN:$000A WRITE OPTN:$000A OPEN DRAIN REGISTER BIT
READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT
READ $0000
EVENT COUNTER SYSTEM
A/D CONVERTER SYSTEM RESEt (RST)
INTERNAL HC05 DATA BUS
Figure 7-3. Port A4/AD0/EVI I/O Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 51
Input/Output Ports (I/O)
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN:$000A WRITE OPTN:$000A OPEN DRAIN REGISTER BIT
READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT
READ $0000
A/D CONVERTER SYSTEM INTERNAL HC05 DATA BUS RESET (RST)
Figure 7-4. Port A5/AD1 I/O Circuitry
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN:$000A WRITE OPTN:$000A OPEN DRAIN REGISTER BIT
READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT
READ $0000
TIME BASE SYSTEM INTERNAL HC05 DATA BUS RESEt (RST)
Figure 7-5. Port A6/RMO I/O Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 52 Freescale Semiconductor
Port A
READ OPTN:$0008 WRITE OPTN:$0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN:$000A WRITE OPTN:$000A OPEN DRAIN REGISTER BIT
READ OPTN:$0000 WRITE OPTN:$0000 DATA DIRECTION REGISTER BIT I/O PIN
WRITE $0000
DATA REGISTER BIT
OUTPUT
READ $0000 INTERNAL HC05 DATA BUS RESET (RST)
Figure 7-6. Port A7 I/O Circuitry
7.2.1 Port A Data Register
Address: Read: Write: Reset: $0000 Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0
Unaffected by Reset
Figure 7-7. Port A Data Register Each port A I/O pin has a corresponding bit in the port A data register. When a port A pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port A pin is programmed as an input, any read of the port A data register will return the logic state of the corresponding I/O pin. The port A data register is unaffected by reset.
7.2.2 Port A Data Direction Register
Address: Read: Write: Reset: $0000 Bit 7 DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
Figure 7-8. Port A Data Direction Register Each port A I/O pin may be programmed as an input by clearing the corresponding bit in the DDRA or may be programmed as an output by setting the corresponding bit in the DDRA. The DDRA can be accessed at address $0000 of the option map. The DDRA is cleared by reset.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 53
Input/Output Ports (I/O)
7.2.3 Port A Pullup Register
Each port A pin may have a software programmable pullup device enabled by the RCR select bits RAH and RAL. The pullup is activated whenever the corresponding bit in the RCR is set. Since reset clears the RCR, all pins will initialize with the pullup devices disabled. See 7.5.6 Resistor Control Register 1.
7.2.4 Port A Wired-OR Mode Register
Port A bits 0:3 configured for output pins are wired-OR mode (open drain) only. Port A bits 4:7 configured for output pins may have software programmable wired-OR mode (open drain) output enabled by the AWOM bit in the WOMR. Since reset clears the WOMR, the wired-OR mode is disabled on reset. See 7.5.8 Open Drain Output Control Register.
7.2.5 Key Wakeup Interrupt (KWI)
Four key wakeup inputs (KWI0:KWI3) share pins with port A. Each key wakeup input is enabled by the corresponding bit in the KWIEN register which resides in the option map. KWI is enabled by the KWIE bit in the INTCR. When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit in the INTSR is set and KWI is generated if KWIE = 1. Each input has a latch which responds only to the falling edge at the pin. All input latches are cleared at the same time by clearing the KWIF bit. See Figure 7-9.
MC68HC05L25 Data Sheet, Rev. 3.1 54 Freescale Semiconductor
Port A
KWIE0
H KWI0
D C R
Q
KWIE1
H KWI1
D C R
Q
KWIE2
H KWI2
D C R
Q
READ KWIF
KWIE3
S Q KWIF R
DATA BUS
H KWI3
D C R
Q
RESET/POR WRITE 1 TO RKWIF KWI KWIE
Figure 7-9. Key Wakeup Interrupt (KWI)
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 55
Input/Output Ports (I/O)
7.2.6 I/O Pin Truth Tables
Table 7-1 through Table 7-6 summarize the input or output mode programming for port A. Table 7-1. PA0-PA2/KWI0-KWI2 I/O Pin Functions
Output Latch KWIE0- KWIE2 Access to DDRA0- DDRA2 Read/Write 0 0 0 0 1 1 1 1 1 1
1. 2.
DDR
RAL
I/O Pin Modes
Access to Data Register Latch PA0-PA2 Read Pin Pin Pin Pin Latch Latch Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin
X X X X 0 1 1 0 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 X 0 1 X 0 1
IN, Hi-Z, KWI Disable IN, KWI Disable, Pullup IN, Hi-Z, KWI Enable IN, KWI Enable, Pullup OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup OUT, OD, KWI Enable OUT, OD, Hi-Z, KWI Enable OUT, OD, Pullup, KWI Enable
DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2 DDRA0- DDRA2
X is don't care state. Does not affect input, but stored to data register latch
MC68HC05L25 Data Sheet, Rev. 3.1 56 Freescale Semiconductor
Port A
Table 7-2. PA3/KWI3/BZ I/O Pin Functions
DDR Output Latch X X X X 0 1 1 0 1 1 X X X X
1. 2.
KWIE3
BZPE
RAL
I/O Pin Modes IN, Hi-Z, KWI Disable IN, Hi-Z, KWI Disable, Pullup IN, Hi-Z, KWI Enable IN, Hi-Z, KWI Enable, Pullup Port OUT, OD, KWI Disable Port OUT, OD, Hi-Z, KWI Disable Port OUT, OD, KWI Disable, Pullup Port OUT, OD, KWI Enable Port OUT, OD, Hi-Z, KWI Enable Port OUT, OD, Pullup, KWI Enable BZ OUT, OD, KWI Disable BZ OUT, OD, KWI Disable, Pullup BZ OUT, OD, KWI Enable BZ OUT, OD, KWI Enable, Pullup
Access to DDRA3 Read/Write
Access to Data Register Latch PA3 Read Pin Pin Pin Pin Latch Latch Latch Latch Latch Latch Pin Latch Pin Latch Pin Latch Pin Latch Write Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch2 Latch2 Latch2 Latch2
0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 0 1 1 1 0 0 1 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 1 0 1 X 0 1 X 0 1 0 1 0 1
DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3 DDRA3
X is don't care state. Does not affect input, but stored to data register latch
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 57
Input/Output Ports (I/O)
Table 7-3. PA4/AD0/EVI I/O Pin Functions
DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output Latch X X X X X X X X 0 1 1 X 0 1 1 1 X 0 1 1 X 0 1 1 EVCE 0 0 X X X 1 1 0 0 0 0 0 0 X 0 0 1 1 1 1 1 1 1 1 ADON 0 0 1 1 1 X X 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 A/D CH X X 0 1-7 1-7 X X X X X X X X 0 1-7 X X X X X 1-7 1-7 1-7 1-7 AWOM X X X X X X X 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 RAH 0 1 X 0 1 0 1 X X 0 1 X X 0 0 1 X X 0 1 X X 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup A/D IN Port IN, Hi-Z Port IN, Pullup Port IN, Hi-Z, Event In Port IN, Pullup, Event In OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup OUT, CMOS OUT, OD OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup OUT, CMOS, Event In OUT, OD, Event In OUT, OD, Hi-Z, Event In OUT, OD, Event In, Pullup OUT, CMOS, Event In OUT, OD, Event In OUT, OD, Hi-Z, Event In OUT, OD, Event In, Pullup Access to DDRA4 Read/Write DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 DDRA4 Access to Data Register Latch PA4 Read Pin Pin 0 Pin Pin Pin Pin Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin
1. X is don't care state. 2. Does not affect input, but stored to data register latch 3. Do not apply analog voltage to this pin unless the I/O pin mode is set to A/D IN. Excessive current may be drawn if this pin is read as a digital input port while analog voltage is applied.
MC68HC05L25 Data Sheet, Rev. 3.1 58 Freescale Semiconductor
Port A
Table 7-4. PA5/AD1 I/O Pin Functions
DDR 0 0 0 0 0 1 1 1 1 1 1 1 1 Output Latch X X X X X X 0 1 1 X 0 1 1 ADON 0 0 1 1 1 0 0 0 0 1 1 1 1 A/D CH X X 1 0, 2-7 0, 2-7 X X X X X X X X AWOM X X X X X 0 1 1 1 0 1 1 1 RAH 0 1 X 0 1 X X 0 1 X X 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup A/D IN Port IN, Hi-Z Port IN, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup Access to DDRA5 Read/Write DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 DDRA5 Access to Data Register Latch PA5 Read Pin Pin 0 Pin Pin Latch Latch Latch Latch Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin
1. X is don't care state. 2. Does not affect input, but stored to data register latch 3. Do not apply analog voltage to this pin unless the I/O pin mode is set to A/D IN. Excessive current may be drawn if this pin is read as a digital input port while analog voltage is applied.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 59
Input/Output Ports (I/O)
Table 7-5. PA6/RMO I/O Pin Functions
I/O Port DDR 0 0 1 1 1 1 1 1 1 1 1
1. 2. 3. 4.
Remote Carrier Output RMPE X X 0 0 0 0 1 1 1 1 1 RMON X X X X X X 0 0 1 1 1 RPOL X X X X X X 0 1 X X X
AWOM X X 0 1 1 1 0 0 0 1 1
RAH 0 1 X X 0 1 X X X 0 1
I/O Pin Modes Port IN, Hi-Z Port IN, Pullup OUT, Output Latch, CMOS OUT, Output Latch, OD OUT, Output Latch, OD, Hi-Z OUT, Output Latch, OD, Pullup OUT, Remote Idle, CMOS = VSS OUT, Remote Idle, CMOS = VDD OUT, Remote Carrier, CMOS OUT, Remote Carrier, OD/Hi-Z OUT, Remote Carrier, OD/Pullup
Access to DDRA6 Read/Write DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6 DDRA6
Access to Data Register Latch PA6 Read Pin Pin Latch Latch Latch Latch Latch Latch Latch Latch Latch Write Latch3 Latch3 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch3 Latch3 Latch3 Latch3 Latch3
OL X X X 0 1 1 X X X X X
OL = output latch X is don't care state. Does not affect input, but stored to data register latch VSS/Hi-Z = output is either VSS (N-ch on) or Hi-Z (N- and P-ch off) depending on clock pulse
5. VSS/Pullup = output is either VSS (N-ch on) or pullup (resistive) depending on clock pulse
Table 7-6. PA7 I/O Pin Functions
DDR 0 0 1 1 1 1 Output Latch X X X 0 1 1 AWOMH X X 0 1 1 1 RAH 0 1 X X 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup Access to DDRA7 Read/Write DDRA7 DDRA7 DDRA7 DDRA7 DDRA7 DDRA7 Access to Data Register Latch PA7 Read Pin Pin Latch Latch Latch Latch Write Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin
1. X is don't care state. 2. Does not affect input, but is stored to the data register latch
MC68HC05L25 Data Sheet, Rev. 3.1 60 Freescale Semiconductor
Port B
7.3 Port B
Port B is an 8-bit bidirectional port that is shared with LCD frontplane drivers as shown in Figure 7-10. Each port B pin is controlled by the corresponding bits in a data direction register and a data register. The port B data register is located at address $0001. The port B data direction register (DDRB) is located at address $0001 of the option map. Reset clears the DDRB. The port B data register is unaffected by reset. The LCD frontplane drivers are enabled on reset.
READ OPTN: $0008 WRITE OPTN: $0008 PULLUP REGISTER BIT PULLUP LOGIC R PULLUP
READ OPTN: $000A WRITE OPTN: $000A OPEN DRAIN REGISTER BIT
FP LCD SYSTEM LCDCR PBE BIT READ OPTN: $0001 WRITE OPTN: $0001
OUTPUT
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT
WRITE $0001
READ $0001
I/O PIN RESET (RST)
INTERNAL HC05 DATA BUS
Figure 7-10. Port B0:B7/FP24:FP17 I/O Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 61
Input/Output Ports (I/O)
7.3.1 Port B Data Register
Address: Read: Write: Reset: $0001 Bit 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 Bit 0 PB0
Unaffected by Reset
Figure 7-11. Port B Data Register (PORTB) Each port B I/O pin has a corresponding bit in the port B data register. When a port B pin is programmed as an output, the state of the corresponding data register bit determines the state of the output pin. When a port B pin is programmed as an input, any read of the port B data register will return the logic state of the corresponding I/O pin. The port B data register is unaffected by reset.
7.3.2 Port B Data Direction Register
Address: Read: Write: Reset: Option -- $0001 Bit 7 DDRB7 6 DDRB6 5 DDRB5 4 DDRB4 3 DDRB3 2 DDRB2 1 DDRB1 Bit 0 DDRB0
Unaffected by Reset
Figure 7-12. Port B Data Direction Register (DDRB) Each port B I/O pin can be programmed as an input by clearing the corresponding bit in the DDRB or programmed as an output by setting the corresponding bit in the DDRB. The DDRB can be accessed at address $0001 of the option map. The DDRB is cleared by reset.
7.3.3 Port B Pullup Register
Each port B pin may have a software programmable pullup device enabled by the RCR select bits RBH and RBL. The pullup is activated whenever the corresponding bit in the RCR is set. Since reset clears the RCR, all pins will initialize with the pullup devices disabled. See 7.5.6 Resistor Control Register 1. NOTE Do not turn on port B pullups when LCD is selected for corresponding port pin.
7.3.4 Port B Wire-ORed Mode Register
Port B bits 0-7 configured for output pins may have software programmable wired-OR mode (open drain) output enabled by the BWOMH and BWOML bits in the WOMR. Since reset clears the WOMR, the wired-OR mode becomes disabled on reset. See 7.5.8 Open Drain Output Control Register.
MC68HC05L25 Data Sheet, Rev. 3.1 62 Freescale Semiconductor
Port B
7.3.5 I/O Pin Truth Tables
Table 7-7 and Table 7-8 summarize the input or output and LCD mode programming for port B. Table 7-7. PB0-PB3/FP24-FP21 I/O Pin Functions
Output Latch X X X X X 0 1 1 LCDCR PBEL 0 0 1 1 1 1 1 1 Access to DDRB0- DDRB3 Read/Write X X 0 0 1 1 1 1 X X X X 0 1 1 1 0 1 0 1 X X 0 1 LCD FP Output LCD FP Output, Pullup3 Port IN, Hi-Z Port IN, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 DDRB0-DDRB3 Access to Data Register Latch PB0-PB3 Read 0 0 Pin Pin Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin
DDR
BWOML
RBL
I/O Pin Modes
1. X is don't care state. 2. Does not affect input, but is stored to data register latch 3. Do not turn on pullup R (RBL = 1) when using these pins as LCD ports.
Table 7-8. PB4-PB7/FP20-FP17 I/O Pin Functions
Output Latch X X X X X 0 1 1 LCDCR PBEH 0 0 1 1 1 1 1 1 Access to DDRB4- DDRB7 Read/Write X X 0 0 1 1 1 1 X X X X 0 1 1 1 0 1 0 1 X X 0 1 LCD FP Output LCD FP Output, Pullup3 Port IN, Hi-Z Port IN, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 DDRB4-DDRB7 Access to Data Register Latch PB4-PB7 Read 0 0 Pin Pin Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin
DDR
BWOMH
RBH
I/O Pin Modes
1. X is don't care state. 2. Does not affect input, but is stored to data register latch 3. Do not turn on pullup R (RBH = 1) when using these pins as LCD ports.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 63
Input/Output Ports (I/O)
7.4 Port C
Port C is a 4-bit I/O port which shares its pins with external interrupt IRQ and the serial peripheral interface (SPI) system as shown in Figure 7-13 through Figure 7-16. Each port C pin is controlled by the corresponding bits in a wired-OR mode register and a pullup register. The port C data register is located at address $0002. The port C pullup register (RCR) is located at address $0009 of the option map. The wired-OR mode register (WOMR) is located at address $000A of the option map. Reset clears the RCR and the WOMR. The PC0-PC2 pins are shared with the serial peripheral interface (SPI). When the SPI is enabled (SPE = 1), the pins PC0, PC1, and PC2 are configured as serial clock output or input (SCK), serial data output (SDO), and serial data input (SDI) pins, respectively. The direction of the SCK depends on the MSTR bit in the SPCR. When PORTC is read, the pin state is read. See Table 7-9 through Table 7-10. The SCK pin should be at the VDD level before the SPI is enabled. The PC3 pin is shared with the external interrupt IRQ pin. The IRQ pin has a Schmitt trigger to improve noise immunity. The PC3 pin state can be read any time regardless of the IRQ configurations. Port C bits 2 and 3, when configured as output ports, are open drain outputs.
READ OPTN: $0009 WRITE OPTN: $0009 PULLUP REGISTER BIT
PULLUP LOGIC
R PULLUP
SPI SYSTEM
MSTR SCK OUT SCK IN OUTPUT
READ OPTN: $000A WRITE OPTN: $000A OPEN DRAIN REGISTER BIT
READ OPTN: $0002 WRITE OPTN: $0002
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN
WRITE $0002
READ $0002 INTERNAL HC05 DATA BUS RESET (RST)
Figure 7-13. Port PC0/SCK Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 64 Freescale Semiconductor
Port C
READ OPTN: $0009 WRITE OPTN: $0009 PULLUP REGISTER BIT
PULLUP LOGIC
R PULLUP
SPI SYSTEM
SDO
OUTPUT
READ OPTN: $000A WRITE OPTN: $000A OPEN DRAIN REGISTER BIT READ OPTN: $0002 WRITE OPTN: $0002 DATA DIRECTION REGISTER BIT WRITE $0002 DATA REGISTER BIT READ $0002 INTERNAL HC05 DATA BUS RESET (RST) OUTPUT I/O PIN
Figure 7-14. PC1/SDO Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 65
Input/Output Ports (I/O)
READ OPTN: $0009 WRITE OPTN: $0009 PULLUP REGISTER BIT PULLUP LOGIC
R PULLUP
SPI SYSTEM READ OPTN: $000A OPEN DRAIN REGISTER BIT READ OPTN: $0002 WRITE OPTN: $0002
SDI
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT* I/O PIN
WRITE $0002
READ $0002 INTERNAL HC05 DATA BUS RESET (RST) *NOTE: Open Drain Output
Figure 7-15. PC2/SDI Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 66 Freescale Semiconductor
Port C
READ OPTN: $0009 WRITE OPTN: $0009 PULLUP REGISTER BIT R PULLUP
TO INTERRUPT SYSTEM S READ $0009 Q Q IRQF R R C D
READ $0008 WRITE $0008
IRQ ENABLE BIT
READ OPTN: $000A OPEN DRAIN REGISTER BIT READ OPTN: $0002 WRITE OPTN: $0002
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT* I/O PIN
WRITE $0002
READ $0002 *NOTE: Open Drain Output INTERNAL HC05 DATA BUS RESET (RST)
Figure 7-16. PC3/IRQ Circuitry
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 67
Input/Output Ports (I/O)
7.4.1 Port C Data Register
Each port C input pin has a corresponding bit in the port C data register. Regardless of the peripheral configuration, any read of the port C data register will return the logic state of the corresponding I/O pin. The port C data register is unaffected by reset.
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented $0002 Bit 7 0 6 0 5 0 4 0 3 PC3 U U = Unaffected 2 PC2 U 1 PC1 U Bit 0 PC0 U
Figure 7-17. Port C Data Register (PORTC)
7.4.2 Port C Data Direction Register
Each port C I/O pin can be programmed as an input by clearing the corresponding bit in the DDRC or programmed as an output by setting the corresponding bit in the DDRC. The DDRC can be accessed at address $0002 of the option map. The DDRC is cleared by reset.
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented Option -- $0002 Bit 7 0 6 0 5 0 4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
Figure 7-18. Port C Data Direction Register (DDRC)
7.4.3 Port C Pullup Register
Each port C pin can have a software programmable pullup device enabled by the RCR2 select bit RC. The pullup is activated whenever the RC bit in the RCR2 is set. Since reset clears the RCR2, all pins will initialize with the pullup devices disabled. See 7.5.7 Resistor Control Register 2.
7.4.4 Port C Wired-OR Mode Register
Port C bits 0 and 1 are configured for output pins and can have software programmable wired-OR mode (open drain) output enabled by the CWOM bit in the WOMR. Since reset clears the WOMR, the wired-OR mode is disabled on reset. Port C bits 2 and 3, when configured as an output port, have wired-OR mode output only. See 7.5.8 Open Drain Output Control Register.
7.4.5 I/O Pin Truth Tables
Table 7-9 through Table 7-12 summarize the input, pullup, wired-OR mode, and SPI pin programming.
MC68HC05L25 Data Sheet, Rev. 3.1 68 Freescale Semiconductor
Port C
Table 7-9. PC0/SCK I/O Pin Functions
DDR 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 Output Latch X X X 0 1 1 X X X X X X X X X X SPCR SPE 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 SPCR MSTR X X X X X X 0 0 1 1 1 1 1 1 1 1 WOMR CWOM X X 0 1 1 1 X X 0 0 0 0 1 1 1 1 RCR2 RC Bit 0 1 X X 0 1 0 0 0 1 0 1 0 1 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup OUT, CMOS OUT, OD OUT, OD, Hi-Z OUT, OD, Pullup SCK IN, Hi-Z SCK IN, Hi-Z SCK OUT, CMOS, Hi-Z SCK OUT, CMOS, Pullup SCK OUT, CMOS, Hi-Z SCK OUT, CMOS, Pullup SCK OUT, OD, Hi-Z SCK OUT, OD, Pullup SCK OUT, OD, Hi-Z SCK OUT, OD, Pullup Access to DDRC0 Read/Write DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 DDRC0 Access to Data Register Latch PC0 Read Pin Pin Latch Latch Latch Latch Pin Latch Pin Pin Latch Latch Pin Pin Latch Latch Write Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2
1. X is don't care state. 2. Does not affect input, but stored to data register latch
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 69
Input/Output Ports (I/O)
Table 7-10. PC1/SDO I/O Pin Functions
DDR 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Output Latch X X X 0 1 1 X X X X X X X X SPCR SPE 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WOMR CWOM X X 0 1 1 1 0 0 0 0 1 1 1 1 RCR2 RC Bit 0 1 X X 0 1 0 1 0 1 0 1 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup Port OUT, CMOS Port OUT, OD Port OUT, OD, Hi-Z Port OUT, OD, Pullup SDO OUT, CMOS, Hi-Z SDO OUT, CMOS, Pullup SDO OUT, CMOS, Hi-Z SDO OUT, CMOS, Pullup SDO OUT, OD, Hi-Z SDO OUT, OD, Pullup SDO OUT, OD, Hi-Z SDO OUT, OD, Pullup Access to DDRC1 Read/Write DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 DDRC1 Access to Data Register Latch PC1 Read Pin Pin Latch Latch Latch Latch Pin Pin Latch Latch Pin Pin Latch Latch Write Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2 Latch2
1. X is don't care state. 2. Does not affect input, but stored to data register latch
Table 7-11. PC2/SDI I/O Pin Functions
DDR 0 0 1 1 1 0 0 1 1 Output Latch X X 0 1 1 X X X X SPCR SPE 0 0 0 0 0 1 1 1 1 WOMR CWOM X X X X X X X X X RCR2 RC Bit 0 1 X 0 1 0 1 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup Port OUT, OD Port OUT, OD, Hi-Z Port OUT, OD, Pullup SDI IN, Hi-Z SDI IN, Pullup SDI IN, Hi-Z SDI IN, Pullup Access to DDRC2 Read/Write DDRC2 DDRC2 DDRC2 DDRC2 DDRC2 DDRC2 DDRC2 DDRC2 DDRC2 Access to Data Register Latch PC2 Read Pin Pin Latch Latch Latch Pin Pin Latch Latch Write Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch2 Latch2 Latch2 Latch2
1. X is don't care state. 2. Does not affect input, but stored to data register latch
MC68HC05L25 Data Sheet, Rev. 3.1 70 Freescale Semiconductor
I/O Port Programming
Table 7-12. PC3/IRQ I/O Pin Functions
DDR 0 0 0 0 1 1 1 1 1 1 Output Latch X X X X 0 1 1 0 1 1 INTCR IRQE 0 0 1 1 0 0 0 1 1 1 WOMR CWOM X X X X X X X X X X RCR2 RC Bit 0 1 0 1 X 0 1 X 0 1 I/O Pin Modes Port IN, Hi-Z Port IN, Pullup Port IN, Hi-Z, IRQ Port IN, Pullup, IRQ Port OUT, OD Port OUT, OD, Hi-Z Port OUT, OD, Pullup Port OUT, OD, IRQ Port OUT, OD, Hi-Z, IRQ Port OUT, OD, Pullup, IRQ Access to DDRC3 Read/Write DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 DDRC3 Access to Data Register Latch PC3 Read Pin Pin Pin Pin Latch Latch Latch Latch Latch Latch Write Latch2 Latch2 Latch2 Latch2 Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin Latch, Pin
1. X is don't care state. 2. Does not affect input, but stored to data register latch
7.5 I/O Port Programming
All bidirectional I/O pins can be programmed as inputs or outputs.
7.5.1 Pin Data Direction
The direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. The data direction bits DDRA0:DDRA7, DDRB0:DDRB7, and DDRC0:DDRC3 are read/write bits which can be manipulated with read-modify-write instructions. At power-on or reset, all DDRs are cleared, which configures all I/O port pins as input (except port B is configured as an LCD port).
7.5.2 Output Pin
When an I/O pin is programmed as an output pin, the state of the corresponding data register bit will determine the state of the pin. The state of the data register bits can be altered by writing to address $0000 for port A, address $0001 for port B, and address $0002 for port C. Reads of the corresponding data register bit at address $0000 or $0003 will return the state of the data register bit (not the state of the I/O pin itself). Therefore, bit manipulation is possible on all pins programmed as outputs.
7.5.3 Input Pin
When an I/O pin is programmed as an input pin, or for an input-only pin, the state of the pin can be determined by reading the corresponding data register bit. Any writes to the corresponding data register bit for an input-only pin will be ignored. If the corresponding bit in the pullup register is set, the input pin will have an activated pullup device. Since the pullup register bits are read-write, bit manipulation may be used on these register bits.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 71
Input/Output Ports (I/O)
7.5.4 I/O Pin Transitions
A glitch can be generated on an I/O pin when changing it from an input to an output unless the data register is first pre-conditioned to the desired state before changing the corresponding DDR bit from a zero to a one.
7.5.5 I/O Pins with Subsystems
An I/O pin that is shared with another subsystem is in general configured as an input pin during reset, except for LCD driver pins. The LCD driver output pins BP0:BP3 and FP0:FP24 are configured to output VDD level during and after reset. See truth tables of each I/O port for more details. Table 7-13. Port Control Register Bits Summary
Port Bit 0 1 2 A 3 4 5 6 7 0 1 2 B 3 4 5 6 7 0 C 1 2 3 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 CWOM 1 1 RC SPE IRQE BWOMH RBH LCDE, PBEH BWOML RBL LCDE, PBEL AWOM RAH WOM 1 1 1 1 RAL KWIE BZPE, KWIE ADON, EVCE ADON RME -- Pullup R Module Control KWIE0 KWIE1 KWIE2 BZxx, KWIE3 CH2:CH0/EVxx CH2:CH0 TBCLK, RMC4:RMC0 -- F24B3:F24B0 F23B3:F23B0 F22B3:F22B0 F21B3:F21B0 F20B3:F20B0 F19B3:F19B0 F18B3:F18B0 F17B3:F17B0 MSTR, SPR DORD, SPR IRQS Module KWI0 KWI1 KWI2 KWI3/BZ AD0/EVI AD1 RMO -- FP24 FP23 FP22 FP21 FP20 FP19 FP18 FP17 SCK SDO SDI IRQ
1. Pullup resistor resistances are typical values with VDD = 3 V. See Chapter 15 Electrical Specifications for more details. 2. Port C bits 2 and 3 are open-drain outputs and do not have CMOS drive capability.
MC68HC05L25 Data Sheet, Rev. 3.1 72 Freescale Semiconductor
I/O Port Programming
7.5.6 Resistor Control Register 1
Address: Read: Write: Reset: 0 0 0 0 = Unimplemented Option -- $0008 Bit 7 0 6 0 5 0 4 0 3 RBH 0 2 RBL 0 1 RAH 0 Bit 0 RAL 0
Figure 7-19. Resistor Control Register 1 (RCR1) Bits 7-4 -- Reserved These bits are not used and always read as zero. RBH -- Port B Pullup Resistor (H) When this bit is set, the pullup resistor is connected to the upper four bits of port B. However, for those pins configured as CMOS output or open-drain output with output of logic low, the pullup resistors are disabled. This bit is cleared on reset. RBL -- Port B Pullup Resistor (L) When this bit is set, the pullup resistor is connected to the lower four bits of port B. However, for those pins configured as CMOS output or open-drain output with output of logic low, the pullup resistors are disabled. This bit is cleared on reset. RAH -- Port A Pullup Resistor (H) When this bit is set, the pullup resistor is connected to the upper four bits of port A. However, for those pins configured as CMOS output or open-drain output with output of logic low, the pullup resistors are disabled. This bit is cleared on reset. RAL -- Port A Pullup Resistor (L) When this bit is set, the pullup resistor is connected to the lower four bits of port A. However, for those pins configured as CMOS output or open-drain output with output of logic low, the pullup resistors are disabled. This bit is cleared on reset.
7.5.7 Resistor Control Register 2
Address: Read: Write: Reset: 0 0 0 0 0 0 0 = Unimplemented Option -- $0009 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 RC 0
Figure 7-20. Resistor Control Register 2 (RCR2) Bits 7:1 -- Reserved These bits are not used and always read as zero. RC -- Port C Pullup Resistor When the RC bit is set, the pullup resistor is connected to all four bits of port C. However, for those pins configured as CMOS output or open-drain output with output of logic low, the pullup resistors are disabled. This bit is cleared on reset.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 73
Input/Output Ports (I/O)
7.5.8 Open Drain Output Control Register
Address: Read: Write: Reset: Option -- $000A Bit 7 BWOMH 0 6 BWOML 0 5 0 0 4 0 0 3 0 0 2 CWOM 0 1 AWOM 0 Bit 0 0 0
= Unimplemented
Figure 7-21. Wired-OR Mode Register (WOM) BWOMH -- Port B Open-Drain Mode (H) When this bit is set, the upper four bits (7-4) of port B pins that are configured as outputs become open-drain outputs. This bit is cleared on reset. BWOML -- Port B Open-Drain Mode (L) When this bit is set, the lower four bits (3-0) of port B pins that are configured as outputs become open-drain outputs. This bit is cleared on reset. Bits 5-3 -- Reserved These bits are not used and always read zero. CWOM -- Port C Open-Drain Mode When this bit is set, port C pins that are configured as outputs become open-drain outputs. This bit is cleared on reset. AWOM -- Port A Open-Drain Mode (High Nibble) When this bit is set, the upper four bits of port A that are configured as outputs become open-drain outputs. This bit is cleared on reset. Bit 0 -- Reserved This bit is not used and always returns to zero.
MC68HC05L25 Data Sheet, Rev. 3.1 74 Freescale Semiconductor
Chapter 8 Oscillators and Clock
8.1 Introduction
The MC68HC05L25 has dual on-chip oscillators for typical 4.0-MHz and 32.768-kHz crystals. Refer to Figure 8-1. The clock generated is used by the CPU and by the subsystem modules such as time base and LCD. Refer to Figure 8-3.
8.2 OSC Clock Divider and POR Counter
The OSC clock is divided by a 7-bit counter which is used for the system clock, time base, and POR counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and clock divided by 128 is provided for the time base and POR counter. The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this counter is used for setting FTUP bit, release of power-on reset (POR), and resuming operation from stop mode. The 7-bit divider and POR counter are initialized to $0078 by these conditions: * Power-on detection * When FOSCE bit is cleared
8.3 System Clock Control
The system clock is provided for all internal modules except time base. Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in the MISC register. By default, OSC divided by two is selected on reset. Table 8-1. System Bus Frequency Selection
SYS1 0 0 1 1 SYS0 0 1 0 1 Divide Ratio OSC Divided by 2 (Default) OSC Divided by 4 OSC Divided by 64 XOSC Divided by 2 CPU Bus Frequency (Hz) OSC = 4.0 M 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M 2.0972 M 1.0486 M 65.536 k -- XOSC = 32.768 K -- -- -- 16.384 k
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 75
Oscillators and Clock
8.4 OSC and XOSC
The secondary oscillator (XOSC) runs continuously after power-up. The main oscillator (OSC) can be stopped to conserve power via the STOP instruction or clearing the FOSCE bit in the MISC register. The effects of restarting the OSC will vary depending on the current state of the MCU, including SYS0-SYS1 and FOSCE bits. NOTE Do not switch the system clock to XOSC (SYS1-SYS0 = 11) when XOSC clock is not available. XOSC clock is available when STUP flag is set. Do not switch the system clock to OSC (SYS1-SYS0 = 00, 01, or 10) when OSC clock is not available. OSC clock is available when FTUP flag is set.
8.5 OSC On Line
If the system clock is OSC, FOSCE should remain set. Executing the STOP instruction in this condition will halt OSC, put the MCU into a low-power mode and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ or RESET re-starts the oscillator. When the POR counter overflows, internal reset is released and execution can begin. The stabilization time will vary between 8064 and 8192 counts. NOTE Exiting STOP with external IRQ will always return the MCU to the state as defined by the register definitions prior to executing the STOP instruction.
OSC OSC1 Rf MASK OPTION ON CHIP OFF CHIP OSC2 XOSC1
XOSC XOSC2
Rxf Rxd
MASK OPTION
Figure 8-1. OSC1, OSC2, XOSC1, and XOSC2 Mask Options
8.6 XOSC On Line
If XOSC is the system clock (SYS0-SYS1 = 1-1), OSC can be stopped either by the STOP instruction or by clearing the FOSCE bit. The suboscillator (XOSC) never stops except during powerdown. This clock can also be used as the clock source of the system clock and time base.
MC68HC05L25 Data Sheet, Rev. 3.1 76 Freescale Semiconductor
XOSC On Line
OSC and XOSC pins have options for feedback and damping resistor implementations. These options are set through mask option and can be read through the MOSR register.
8.6.1 XOSC with FOSCE = 1
If the system clock is XOSC and FOSCE = 1, executing the STOP instruction will halt OSC, put the MCU into a low-power mode, and clear the 6-bit POR counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ re-starts the oscillator; however, execution begins immediately using XOSC. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will vary between 8064 and 8192 counts.
8.6.2 XOSC with FOSCE = 0
If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR counter to $0078. Execution will continue with XOSC and when FOSCE is set again, OSC will re-start. When the POR counter overflows, FTUP is set, signaling that OSC is stable and OSC can be used as the system clock. The stabilization time will be 8072 counts.
8.6.3 XOSC with FOSCE = 0 and STOP
If XOSC is the system clock and FOSCE is cleared, further power reduction can be achieved by executing the STOP instruction. In this case, OSC is stopped, the 7-bit divider and 6-bit POR counter are preset to $0078 (since FOSCE = 0), and execution is halted. Exiting STOP with external IRQ does not re-start the OSC; however, execution begins immediately using XOSC. OSC can be re-started by setting FOSCE, and when the POR counter overflows, FTUP be will set, signaling that OSC is stable and can be used as the system clock. The stabilization time will be 8072 counts.
8.6.4 Unused XOSC
When XOSC is not used, the XOSC1 pin must be connected to the RESET pin to ensure proper initialization of clock circuitry. The XOSC2 pin should be left unconnected. See Figure 8-2. Configure time base by setting the TBCLK bit in TBCR1 to receive clock from fast oscillator OSC. NOTE When XOSC is not used, the XOSC1 input pin should be connected to RESET pin to ensure proper initialization of clock circuitry.
RESET LOGIC RESET ON CHIP OFF CHIP FROM EXTERNAL RESET CIRCUIT XOSC1
XOSC XOSC2
NO CONNECT
Figure 8-2. Unused XOSC1 Pin
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 77
Oscillators and Clock
8.7 Stop and Wait Modes
During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator (XOSC) is disconnected, such that all modules except time base are halted. Entering stop mode clears the FTUP flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ, KWI, SPI (slave mode), or TBI interrupt. If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the POR counter, and this overflow also sets FTUP status flag. If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for exiting stop mode because XOSC never stops, and re-start of main oscillator depends on FOSCE bit. During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode is exited by the RESET and any interrupts. Table 8-2. CPU Startup Time Requirements
Before RESET or Interrupt CPU Clock Source -- OSC (OSC ON) CPU -- RUN RUN OSC (OSC OFF) STOP STOP XOSC (OSC ON) XOSC (OSC OFF) RUN RUN STOP STOP
1. Do not enter this state. 2. This state does not exist.
FOSCE -- 1 01 1 02 1 0 1 0
Power-On Reset Delay -- -- -- -- -- -- -- --
External RESET -- No Delay Delay Delay Delay No Delay Delay Delay Delay
Exit Stop Mode by an Interrupt -- -- -- Delay Delay -- -- No Delay No Delay
NOTE Power-on reset is strictly for power-on conditions and does not detect a drop in power.
8.8 XOSC Clock Divider and POD Counter
The XOSC clock divided by a 14-bit counter, also called power-on divider (POD), is used for the system clock. The oscillator clock divided by two is used by the system clock and oscillator clock divided by 64 or 128 is provided for the LCD module. The overflow of the POD counter is used for setting the STUP bit and releasing power-on reset (POR). The 14-bit divider/POD counter is initialized to $0078 by power-on detection.
8.9 System Clock Control
The system clock (PH2) is provided for CPU and all internal modules.
MC68HC05L25 Data Sheet, Rev. 3.1 78 Freescale Semiconductor
System Clock Control
1/3
0 1
1 SEL 1/2 0 SEL
PORT A6
REMOTE CONTROL CARRIER OUTPUT
TIME BASE CONTROL REGISTER 1 ($10)
TBCLK
0
LCLK
RMC4 RMC3 RMC2 RMC1 RMC0
RF
OSC2
OSC
LSB
7-BIT DIVIDER #1 1/32 1/64
1/16
1/2
1/4
1/8
OSC1
SEL
MSB
X1 C1 C2 TIME BASE CLOCK (TBCLK) 6-BIT DIVIDER XOSC1 RXF XOSC SEL LSB (0 0 0 SEL 1
01 10 SEL 00 11
1/2 0 SEL
SYSTEM CLOCK (PH2)
0 1/128 1/64
1
LCD Clock (LCDCLK)
XOSC2
7-BIT DIVIDER #2 0 1 1 SEL 1
MSB 1) POL BUZZER OUTPUT
RXD X2 C3 C4 (0 LSB 0 0 0 0 0 0) MSB 1/128 1/64 FTUP STUP 0 0 SYS1
7-BIT DIVIDER #3 1/32
SYS0 FOSCE OPTM
MISC REGISTER ($3E)
11 10 SEL 01 00 F-F
1/4
COP RESET (COPR)
TBIF
TBIE
TBR1
TBR0
RTBIF
--
COPE COPC
TIME BASE CONTROL REGISTER 2 ($11)
Figure 8-3. Clock Signal Distribution
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 79
Oscillators and Clock
8.10 XOSC
The oscillator (XOSC) runs continuously after power-up. The XOSC never stops while power is applied. XOSC pins have options for feedback and damping resistor implementations. These options are set through mask option and may be read through the mask option status register (MOSR). See 1.3 Mask Options.
8.11 Stop and Wait Modes
Power reduction can be achieved by executing the STOP instruction and halting the CPU. During stop mode, the CPU and all modules except time base are halted. The stop mode is exited by external RESET, COP reset, IRQ, SPI (slave mode), or TB interrupt. The CPU resumes immediately from stop mode since XOSC never stops oscillating during stop mode. The CPU clock is halted and the peripheral modules are not affected during wait mode. Wait mode is exited by RESET or any interrupts. Table 8-3. Recovery Time Requirements
Mode Before Reset or Interrupt Power Off Run Stop/Wait Delay Time After Reset or Interrupt Power-On Reset Delay See Note See Note COP and External RESET -- No Delay No Delay Exit Stop Mode by Interrupt -- -- No Delay
NOTE: Power-on reset is strictly for power-on conditions and does not detect a drop in power.
8.12 Miscellaneous Register
Address: Read: Write: Reset: U U 0 0 = Unimplemented $003E Bit 7 FTUP 6 STUP 5 0 4 0 3 SYS1 0 U = Unaffected 2 SYS0 0 1 FOSCE 1 Bit 0 OPTM 0
Figure 8-4. Miscellaneous Register (MISC) FTUP -- OSC Time Up Flag Power-on detection and clearing FOSCE bit clears this bit. This bit is set by the overflow of the POR counter. A reset does not affect this bit. Read: 1 = OSC clock available for the system clock 0 = During POR or OSC shut down
MC68HC05L25 Data Sheet, Rev. 3.1 80 Freescale Semiconductor
Miscellaneous Register
STUP -- XOSC Time Up Flag The power-on detection clears this bit. This bit is set after the time base has counted 16,264 clocks. A reset does not affect this bit. Read: 1 = XOSC clock available for the system clock 0 = XOSC is not stabilized or no signal on XOSC1 and XOSC2 pins Bits 5 and 4 -- Reserved These bits are not used and always read as zero. SYS1 and SYS0 -- System Clock Select These two bits select the system clock source. On reset the SYS1 and SYS0 bits are initialized to zero and zero, respectively. Table 8-4. System Bus Frequency Selection
SY S1 0 0 1 1 SY S0 0 1 0 1 Divide Ratio OSC Divided by 2 (Default) OSC Divided by 4 OSC Divided by 64 XOSC Divided by 2 2 CPU Bus Frequency (Hz) OSC = 4.0 M 2.0 M 1.0 M 62.5 k -- OSC = 4.1943 M 2.0972 M 1.0486 M 65.536 k -- XOSC = 32.768 k -- -- -- 16.384 k
NOTE Do not switch the system clock to XOSC (SYS1-SYS0 = 11) when the XOSC clock is not available. The XOSC clock is available when the STUP flag is set. Do not switch the system clock to OSC (SYS1-SYS0 = 00, 01, or 10) when the OSC clock is not available. OSC clock is available when the FTUP flag is set. FOSCE -- Fast (Main) Oscillator Enable The FOSCE bit controls the main oscillator activity. This bit should not be cleared by the CPU when the main oscillator is selected as the system clock source. This bit is set on reset. 1 = When this bit is set: 1. The main oscillator starts again. 2. The FTUP flag is set by the POR counter overflow (8072 clocks) and OSC is ready to be used as the system and time base clocks. 0 = When this bit is cleared: 1. OSC is shut down. 2. The 7-bit dividers at the OSC input and POR counter are initialized to $0078. 3. The FTUP flag is cleared. OPTM -- Option Map Select The OPTM bit selects one of two register maps at $0000-$000F. This bit is cleared on reset. 1 = Option map selected 0 = Main register map selected
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 81
Oscillators and Clock
STATE A
CPU:RUN 2:OSC/2 OSC:ON XOSC:ON STATE C CPU:RUN 2:OSC/64 OSC:ON XOSC:ON RESET INT
STATE B CPU:RUN 2:OSC/4 OSC:ON XOSC:ON
STATE A STATE B STATE C
CPU:RUN 2:XOSC/2 OSC:ON XOSC:ON STATE D RESET, INT FOSCE = 0 WHEN STUP = 1 FOSCE = 1 WHEN FTUP = 1 DELAY
STOP
STOP
POWER ON CPU:RUN 2:XOSC/2 OSC:OFF XOSC:ON STATE E
INT RESET
STOP
HIGH SPEED A B INT STATE D STATE E
2 = BUS CLOCK
C D E STOP LOW POWER
NOTES: 1. When switching from state E to state D, the FTUP bit in the MISC register must be set. 2. When switching from state D to state E, the STUP bit in the MISC register must be set.
Figure 8-5. Clock State and STOP/POD Delay Diagram
MC68HC05L25 Data Sheet, Rev. 3.1 82 Freescale Semiconductor
Chapter 9 Time Base
9.1 Introduction
Time base is a 14-bit up-counter which is clocked by XOSC. This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 16,264 clocks, the STUP bit in the MISC register is set. See Figure 8-4 for more information.
9.2 Time Base Submodules
The clock divided by the time base is used for LCDCLK, STUP, TBI, and COP. The time base clock can be provided either from OSC or XOSC.
9.2.1 LCDCLK
One of four clock frequency combinations can be selected for the LCD clock. Table 9-1. LCD Clock Frequency
TBCR1 TBCLK LCLK 0 0 1 1 0 1 0 1 XOSC / 64 XOSC / 28 OSC / 8192 OSC / 16,384 Divide Ratio 512 256 244 122 LCD Clock Frequency (Hz) (fXOSC = 32.768 kHz) OSC = 2.0 MHz OSC = 4.0 MHz 512 256 488 244 OSC = 4.1943 MHz 512 256 512 256
9.2.2 STUP
The time base divider is initialized to $0078 at power-on, and when the count reaches 16,264, the STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared while power is applied.
9.2.3 TBI
Time base interrupt can be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz crystal at XOSC pins. See Table 9-2.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 83
Time Base
Time base interrupt flag (TBIF) is set every period and an interrupt is requested if the enable bit (TBIE) is set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the TBR1 and TBR0 bits in the TBCR2 register. Table 9-2. Time Base Interrupt Frequency
TBCR2 TBR1 TBR0 0 0 1 1 0 1 0 1 Divide Ratio TBCLK / 128 TBCLK / 4096 TBCLK / 8192 TBCLK / 16,384 Frequency (Hz) OSC = 4.0 MHz 244 7.63 3.81 1.91 OSC = 4.1943 MHz 256 8.00 4.00 2.00 XOSC = 32.768 kHz 256 8.00 4.00 2.00
9.2.4 COP
The computer operating properly (COP) watchdog timer on the MC68HC05L25 is controlled by the COPE and COPC bits in the TBCR2 register. The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI clock is divided by four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The COP timeout reset has the same vector address as power-on and external RESET. To prevent the COP timeout, the COP divider is cleared by writing a one to the COP clear (COPC) bit. When the time base divider is driven by the OSC clock, the clock for the divider is suspended during stop mode or when FOSCE is equal to zero. This may cause stretching of the COP period or no COP timeout reset occurring when there is a processing error. It is recommended that the XOSC clock be used as the clock source for time base to avoid these problems. When the COP is enabled during stop mode and the time base is driven by the XOSC clock, the divider does not stop counting and the COPC bit must be triggered to prevent the COP timeout. It is recommended that the COP watchdog should be disabled for a system that must have intentional use of the stop mode period longer than the COP timeout period. Table 9-3. COP Timeout Period
TBCR2 TBR1 0 0 1 1 TBR0 0 1 0 1 OSC = 4.0 MHz Min 12.3 393 786 1573 Max 16.4 524 1048 2097 COP Period (ms) OSC = 4.1943 MHz Min 11.7 375 750 1500 Max 15.6 500 1000 2000 XOSC = 32.768 kHz Min 11.7 375 750 1500 Max 15.6 500 1000 2000
MC68HC05L25 Data Sheet, Rev. 3.1 84 Freescale Semiconductor
Time Base Submodules
9.2.5 Remote Control Carrier Generator
The PA6/RMO pin functions as a general-purpose I/O port after reset. The RMPE bit must be set in order to use this port as a remote control carrier output. The RMO outputs idle state is set by the RPOL bit when RMON is cleared. The RMCLK signal selected by RMC4-RMC0 bits is output on the pin when RMON is set. Table 9-4. Remote Carrier Frequency Selection
RMC4 RMC3 RMC2: RMC0 0 1 1 2 3 4 0 5 0 1 0 2 3 4 5 0 1 1 2 3 4 1 5 0 1 0 2 3 4 5 33% 50% 50% 50% RMO Duty Divider OSC = 440 kHz 1/4 1/8 1/16 1/32 1/64 1/128 1/12 1/24 1/48 1/96 1/192 1/384 1/2 1/4 1/8 1/16 1/32 1/64 1/6 1/12 1/24 1/48 1/96 1/192 110 kHz 55.0 kHz 27.5 kHz 13.8 kHz 6.88 kHz 3.44 kHz 36.7 kHz 18.3 kHz 9.17 kHz 4.58 kHz 2.29 kHz 1.15 kHz 220 kHz 110 kHz 55.0 kHz 27.5 kHz 13.8 kHz 6.88 kHz 73.3 kHz 36.7 kHz 18.3 kHz 9.17 kHz 4.58 kHz 2.29 kHz Remote Carrier Frequency on RMO Pin (RMCLK) OSC = 3.6 MHz 900 kHz 450 kHz 225 kHz 113 kHz 56.3 kHz 28.1 kHz 300 kHz 150 kHz 75.0 kHz 37.5 kHz 18.8 kHz 9.38 kHz 1800 kHz 900 kHz 450 kHz 225 kHz 113 kHz 56.3 kHz 600 kHz 300 kHz 150 kHz 75.0 kHz 37.5 kHz 18.8 kHz OSC = 4.0 MHz 1000 kHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 333 kHz 167 kHz 83.3 kHz 41.7 kHz 20.8 kHz 10.4 kHz 2000 kHz 1000 kHz 500 kHz 250 kHz 125 kHz 62.5 kHz 667 kHz 333 kHz 167 kHz 83.3 kHz 41.7 kHz 20.8 kHz
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 85
Time Base
RMCLK PA6 I/O PORT PA6/RMO RMO PORT PA6 I/O PORT
IDLE DDRA6
CARRIER OUT
IDLE
RMPE
RMON
RPOL
Figure 9-1. Remote Control Carrier Output Port Control (RPOL = 1)
RMCLK PA6 I/O PORT PA6/RMO RMO PORT PA6 I/O PORT
IDLE DDRA6
CARRIER OUT
IDLE
RMPE
RMON
RPOL
Figure 9-2. Remote Control Carrier Output Port Control (RPOL = 0)
RMC4 = 0: RPOL = X RMC4 = 1:
RMCLK
RMCLK
Figure 9-3. Remote Control Carrier Duty Control
MC68HC05L25 Data Sheet, Rev. 3.1 86 Freescale Semiconductor
Time Base Submodules
9.2.6 Buzzer Tone Generator
The PA3/KWI3/BZ pin functions as a general-purpose I/O port after reset. The BZPE bit must be set in order to use this port as buzzer tone output. The BZ outputs idle state is set by the BPOL bit when BZON is cleared. The BZCLK signal selected by the BCLK bit is output on the pin when BZON is set. The BZ output pin is open drain. Table 9-5. Buzzer Frequency
Buzzer Frequency on BZ Pin (BZCLK) TBCR1 TBCLK 0 0 1 1 TBCR3BCLK 0 1 0 1 fOSC = 2 MHz fXOSC = 32.768 kHz 4096 Hz 2048 Hz Approximately 1953 Hz Approximately 977 Hz fOSC = 3.6 MHz fXOSC = 32.768 kHz 4096 Hz 2048 Hz Approximately 3516 Hz Approximately 1758 Hz fOSC = 4 MHz fXOSc = 32.768 kHz 4096 Hz 2048 Hz Approximately 3906 Hz Approximately 1953 Hz fOSC = 4.194304 MHz fXOSC = 32.768 kHz 4096 Hz 2048 Hz 4096 Hz 2048 Hz
BZCLK PC2 I/O PORT PA3/BZ* BZ PORT PC2 I/O PORT
IDLE
CLOCK OUT
IDLE
BZPE
BZON
BPOL *The BZ output pin is open drain. The logic 1 shown for the BZ pin is actually a hi-Z state unless it is a pullup.
Figure 9-4. Buzzer Tone Output Control
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 87
Time Base
9.3 Time Base Control Register 1
Address: Read: Write: Reset: $0010 Bit 7 TBCLK 0 6 0 0 5 LCLK 0 4 RMC4 0 3 RMC3 0 2 RMC2 0 1 RMC1 0 Bit 0 RMC0 0
= Unimplemented
Figure 9-5. Time Base Control Register 1 (TBCR1) TBCLK -- Clock Source This bit selects the time base clock source and is cleared on reset. 1 = OSC selected for time base clock source 0 = XOSC selected for the time base clock source Bit 6 -- Reserved This bit is not used and always reads as zero. LCLK -- LCD Clock The LCLK bit selects the clock for the LCD driver and is cleared on reset. When TBCLK = 0: 1 = XOSC divide by 128 selected for the LCD clock 0 = XOSC divide by 64 selected for the LCD clock When TBCLK = 1: 1 = OSC divide by 16,384 selected for the LCD clock 0 = OSC divide by 8192 selected for the LCD clock RMC4 -- Remote Control Generator Divider This bit selects the remote control carrier duty cycle and is cleared on reset. 1 = 33-67% duty selected if RMC3 = 0 0 = 50-50% duty selected RMC3:RMC0 -- Remote Control Generator Divider These bits select the remote control carrier frequency. (See Table 9-4.) These bits are cleared on reset.
MC68HC05L25 Data Sheet, Rev. 3.1 88 Freescale Semiconductor
Time Base Control Register 2
9.4 Time Base Control Register 2
Address: Read: Write: Reset: 0 $0011 Bit 7 TBIF 6 TBIE 0 5 TBR1 0 4 TBR0 0 3 0 RTBIF 0 0 2 0 1 COPE 0 Bit 0 0 COPC 0
= Unimplemented
Figure 9-6. Time Base Control Register 2 (TBCR2) TBIF -- Time Base Interrupt Flag The TBIF bit is set every timeout interval of the time base interrupt. This is a read-only bit and is cleared by writing a one to the RTBIF bit. Reset clears the TBIF bit. The time base interrupt period between reset and first TBIF depends on the time elapsed during reset, since the time base divider is not initialized on reset. TBIE -- Time Base Interrupt Enable The TBIE bit enables the time base interrupt capability. If TBIF = 1 and TBIE = 1, the time base interrupt is generated. 1 = TB interrupt requested when TBIF = 1 0 = TB interrupt disabled TBR1-TBR0 -- Time Base Interrupt Rate Select The TBR1 and TBR0 bits select one of four rates for the time base interrupt period. The TBI rate is also related to the COP timeout reset period. See Table 9-2 and Table 9-3. These bits are set to a logical 1 on reset. RTBIF -- Reset Time Base Interrupt Flag The RTBIF bit is a write-only bit and always reads as zero. Writing a one to this bit clears the TBIF bit and writing zero to this bit has no effect. 1 = Reset TBIF 0 = No effect Bit 2 -- Reserved This bit is not used and always reads as zero. COPE -- COP Enable When the COPE bit is one, the COP reset function is enabled. This bit is cleared on reset (including COP timeout reset) and a write to this bit is allowed only once after reset. 1 = COP enabled 0 = COP disabled COPC -- COP Clear Writing a logical 1 to COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout period depends on the TBI rate.) This is a write-only bit and returns to zero when read. 1 = Clear COP timeout divider 0 = No effect
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 89
Time Base
9.5 Time Base Control Register 3
Address: Read: Write: Reset: 0 $001F Bit 7 0 6 RMON 0 5 RPOL 0 4 RMPE 0 3 BCLK 0 2 BZON 0 1 BPOL 0 Bit 0 BZPE 0
= Unimplemented
Figure 9-7. Time Base Control Register 3 (TBCR3) Bit 7 -- Reserved This bit is not used and always reads as zero. RMON -- Remote Control Generator Signal ON When the port is used as remote control output (RMPE = 1), this bit turns on or off the remote control signal. The idle state is output when cleared and is cleared on reset. 1 = Carrier on 0 = Carrier off; idle state defined by RPOL as output RPOL -- Remote Control Idle Polarity This bit controls the idle state of the remote control generator output on the port and is cleared on reset. 1 = Remote idle state outputs logic 1. 0 = Remote idle state outputs logic 0. RMPE -- Remote Control Generator Port Output Enable This bit enables the remote control generator output on the port. The actual remote signal on/off is controlled by RMON bit. This bit is cleared on reset. 1 = Port pin functions as remote control output. 0 = Port pin functions as general I/O port. BCLK -- Buzzer Clock Select This bit selects the buzzer tone output frequency. This bit is cleared on reset. 1 = OSC/211 or XOSC/24 selected for buzzer clock 0 = OSC/210 or XOSC/23 selected for buzzer clock BZON -- Buzzer Signal ON When the port is used as buzzer output (BZPE = 1), BZON turns on the buzzer signal. Reset clears BZON. 1 = Buzzer on 0 = Buzzer off; idle state defined by BPOL as output BPOL -- Buzzer Output Polarity This bit selects the buzzer output pin's polarity during buzzer idle (standby) period (BZON = 0). When BZE = 0, this bit has no effect. This bit is cleared on reset. 1 = Buzzer idle state outputs logic 1. 0 = Buzzer idle state outputs logic 0. BZPE -- Buzzer Output Port Enable This bit controls whether the port functions as buzzer output or a general I/O port. The actual buzzer signal on/off is controlled by the BZON bit. (See Table 7-1.) This bit is cleared on reset. 1 = Port pin functions as buzzer output. 0 = Port pin functions as general I/O port.
MC68HC05L25 Data Sheet, Rev. 3.1 90 Freescale Semiconductor
Chapter 10 Serial Peripheral Interface
10.1 Introduction
The serial peripheral interface (SPI) is built into the MC68HC05L25 to transmit or receive synchronous serial data. In this format, the serial clock is not included in the data stream and must be provided as a separate signal. When the SPI is enabled, reading port C will return the actual pin level. The MSTR bit selects the source of the serial clock from the internal or the external clock. The internal clock speed is selectable as 1/2 or 1/16 of the system clock.
10.2 Features
* * * * * * * Full Duplex 3-Wire Synchronous Transfers Master or Slave Operation Bit Rate Selection End of Transmission Interrupt Data Collision Flag Master Mode Maximum Serial Clock Speed at 1/2 the CPU System Clock Slave Mode Maximum Serial Clock Speed Up until the CPU System Clock
10.3 Block Diagram
Figure 10-1 illustrates the block diagram of the SPI module.
10.3.1 Control
The control logic is an interface to the HC05 internal bus. It generates the clock start signal, when writing to SPDR is detected in master mode. It also generates a flag clear signal and interrupt request to the CPU.
10.3.2 SPDR
The serial peripheral data register (SPDR) is an 8-bit shift register. This register can be read or written by the CPU. It can also change parallel data to serial or vice versa.
10.3.3 SPCR
The serial peripheral control register (SPCR) contains bits SPIE, SPE, DORD, SPR, and MSTR. The description on each bit can be found in 10.5.1 Serial Peripheral Control Register.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 91
Serial Peripheral Interface
HC05 INTERNAL BUS INTERRUPT CONTROLS & ADDRESS BUS CONTROL LOGIC DATA BUS
000000 SPSR SPCR SPE DORD MSTR
0 SPDR D CK START Q SDO
SPIF DCOL
SPR
R
RESET CLOCK GENERATOR SCK
SDI
. Figure 10-1. SPI Block Diagram
10.3.4 Clock Generator
The clock generator includes a 3-bit serial clock counter. The counter starts after detecting the serial clock and halts after setting SPIF when the counter overflows. In master mode, this block generates serial clock (SCK) when CPU writes to the data register (SPDR) and the clock rate is selected by SPR bit in the control register (SPCR). In slave mode, external clock from the SCK pin is used instead of master mode clock, and SPR has no effect.
10.3.5 Others
The SPI does not use the data register of port C. Therefore, regardless of whether the SPI is used, the data register can be read from port C.
10.3.6 Signal Description
The basic signals SDO, SDI, and SCK of SPI are described in the following paragraphs. SCK, SDO, and SDI pins are shared with port C pins PC0, PC1, and PC2, respectively.
10.3.7 Serial Data Out (SDO)
SDO is an output pin. This pin is shared with port C pin PC1. When the SPI is enabled by SPE bit in the SPCR, this pin becomes an output pin. When the SPE is cleared, the pin becomes PC1 and thus becomes an input pin. The state of PC1/SDO can be read any time through PC1 data register. When the SPI is enabled and PC1/SDO is an output, data output becomes valid at the falling edge of the serial clock.
MC68HC05L25 Data Sheet, Rev. 3.1 92 Freescale Semiconductor
Functional Description
10.3.8 Serial Data In (SDI)
The SDI pin is multiplexed with a general-purpose I/O pin. This becomes an input-only pin and accepts serial input data when the SPI is enabled.
10.3.9 Serial Clock (SCK)
The SCK pin is used for synchronization of both input and output data streams through SDI and SDO pins. The SCK pin should be at VDD level before SPI is enabled. The master and slave devices are capable of exchanging a data byte during a sequence of eight clock pulses. Since SCK is generated by the master, slave data transfer is accomplished by synchronization of SCK. When the MSTR bit in the SPCR is set, SCK becomes an output and the serial clock is supplied to the internal and external systems. When the serial clock is idling, high level is being output. When the bit is a logic 1, the CPU writes data to SPCR and outputs eight clock pulses. After the end of the eighth clock, high level is being output while idling. The clock speed in master mode is one-half the system clock. When the MSTR bit in the SPCR is cleared, SCK becomes an input and the external system supplies the serial clock while the internal system operates by synchronizing to this clock. After eight serial clocks are input to the SCK pin, the SPIF bit in the SPSR is set and will not receive the next serial clock input until the SPIF bit is cleared. The clock speed in slave mode is dependent upon the speed of the external system and has a maximum speed up till the internal system clock.
10.4 Functional Description
A block diagram of the SPI module is shown in Figure 10-1. In the SPI, if the SPE bit (SPI enable) of SPCR is set, bits 0, 1, and 2 of port C will be connected. During this time, bit 0 is used as the SCK (serial clock), bit 1 as the SDO (serial data out), and bit 2 will become SDI. When SPE is a logic zero, SPI system is disabled. In master mode (MSTR = 1), SCK becomes an output. When the CPU writes data to SPDR, start trigger will be applied from the control logic to the clock generator. The clock generator divides the system clock of the CPU (by 2 or 16) to generate the serial clock which is then output to the SCK pin. This clock is also used in the 3-bit clock counter and 8-bit shift register (SPDR). In slave mode (MSTR = 0), SCK becomes an input, and the external serial clock is used. Therefore, the internal clock generator will not generate the serial clock. After detecting the external clock, the clock will be used by the 3-bit clock counter and the 8-bit shift register (SPDR) located in the clock generator. The SCK is used to latch incoming data. In either master or slave mode, the SPIF flag is set after the end of the transmission and if the SPIE bit in the SPCR is set, the interrupt request is sent to the CPU. This interrupt request is accepted when the I mask bit of condition code register (CCR) is a logic zero and is inhibited when the bit is a logic one or until the mask is released. Also, if the SPIE bit is cleared, the interrupt request will not be accepted by the CPU. To clear the SPIF while it is still set, the SPDR must be read or written after accessing SPSR. Regardless of the master/slave I/O conditions, the DCOL bit of SPSR will be set when SPDR is accessed while the shift register is operating and while SPSR is not being accessed with SPIF set. DCOL is used to indicate that the data is not being properly read or written into SPDR. To clear the DCOL flag while it is still set, the SPDR must be read or written after accessing SPSR.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 93
Serial Peripheral Interface
10.5 Register Description
The SPI has three registers: control register (SPCR), status register (SPSR), and data register (SPDR). SPCR and SPDR can be read or written by the CPU, but SPSR can only be read.
10.5.1 Serial Peripheral Control Register
Address: Read: Write: Reset: $000A Bit 7 SPIE 0 6 SPE 0 5 DORD 0 4 MSTR 0 3 0 0 2 0 0 1 0 0 Bit 0 SPR 0
= Unimplemented
Figure 10-2. SPI Control Register (SPCR) SPIE -- SPI Interrupt Enable When SPIE (SPI interrupt enable) is set, it allows the occurrence of processor interrupt when SPIF in the SPSR is set. This interrupt request is accepted when the I bit in the CCR is cleared but inhibited when I bit is set. If the interrupt request is sent repeatedly while the I bit and only when SPIE and SPIF are set, the interrupt will occur immediately after the I bit is cleared. Reset clears this bit. 1 = SPI interrupt enabled 0 = SPI interrupt disabled SPE -- SPI Enable When SPE (SPI enable) is set, it enables the SPI system and connects bit 0 and bit 1 of port C to SCK and SDIO. Clearing SPE initializes the SPI system and disconnects SPI from port C. Reset clears this bit. 1 = SPI enabled 0 = SPI disabled NOTE PC0/SCK should be at VDD level before SPI is enabled. This can be done with an internal or external pullup resistor or by setting DDRC0 = 1 and PC0 = 1 prior to enabling the SPI. Otherwise, the circuit will not initialize correctly. DORD -- Data Transmission Order When DORD is set, the data in the 8-bit shift register (SPDR) is shifted in/out from LSB first. When clear, the data is shifted MSB first. Reset clears this bit. 1 = LSB first 0 = MSB first MSTR -- Master Mode Select This MSTR (master mode select) bit determines whether to output the serial clock internally or input the clock externally. When set, SPI is in master mode and SCK is configured as an output pin. SCK outputs the serial clock when CPU writes data to SPDR. When cleared, the SPI is in slave mode and SCK is configured as an input pin. SCK receives the serial clock externally. Reset clears this bit. 1 = Master mode 0 = Slave mode
MC68HC05L25 Data Sheet, Rev. 3.1 94 Freescale Semiconductor
Register Description
Bits 3:1 -- Reserved These bits are reserved and always read as zero. SPR -- SPI Clock Rate Select This is the clock rate selection bit. When set, the master mode SCK rate is the system clock divided by 16. When clear, the rate system clock is divided by two. Reset clears this bit. 1 = System clock divided by 16 0 = System clock divided by 2
10.5.2 Serial Peripheral Status Register
Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented $000B Bit 7 SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0
Figure 10-3. SPI Status Register (SPSR) SPIF -- Serial Transfer Complete Flag SPIF (serial peripheral interface flag) notifies the user that the data transfer between MC68HC05L25 and the external device has been completed. Upon completion of the data transfer, the rising edge of the eighth serial clock pulse sets SPIF. If SPIE in the SPCR is set, the SPI interrupt (SPII) will be generated. While SPIF is set, all access to the SPDR is inhibited until SPSR is read by the CPU. Also, even if the ninth serial clock is detected, the shift register (SPDR) will not operate. Clearing the SPIF is accomplished by a software sequence of accessing the SPSR while SPIF is set and followed by the SPDR access. (SPIF and DCOL can be cleared simultaneously.) Reset clears this bit. 1 = Serial data transfer complete 0 = Serial data transfer in progress DCOL -- Data Collision DCOL (data collision) notifies the user that an invalid access to the SPDR has been made. This bit is set when an attempt was made to read or write to SPDR while a data transfer was taking place with an external device. When DCOL is set, access to the SPDR becomes invalid. The transfer continues uninterrupted without any effect from the SPDR access. This flag does not generate SPI interrupt. It is read-only. DCOL is cleared by reading the SPSR with SPIF set followed by a read or write to the SPDR. If the last part of the clearing sequence is done after another transmission has started, DCOL will be set again. (DCOL and SPIF can be cleared simultaneously.) Reset clears this bit. 1 = Data collision occurred 0 = Data collision did not occur Bits 5-0 -- Reserved These bits are unused and always read as zero.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 95
Serial Peripheral Interface
10.5.3 SPI Data Register
Address: Read: Write: Reset: $000C Bit 7 SPD7 6 SPD6 5 SPD5 4 SPD4 3 SPD3 2 SPD2 1 SPD1 Bit 0 SPD0
Unaffected by Reset
Figure 10-4. SPI Data Register (SPDR) The SPDR is used to transmit and receive data on the serial bus. In master mode, a write to SPDR initiates the transmission/reception of data byte. At transfer completion, SPIF status bits are set. In slave mode, a write to the SPDR will not initiate the serial clock. The serial clock is input to the SCK pin by the external device. In either master or slave mode, a write to the SPDR is inhibited while this register is shifting (this condition causes DCOL to set) or when SPIF is set without reading SPSR. In this case, even if an access has occurred, the access becomes invalid. Refer to SPIF and DCOL descriptions for more information. When SPI is not being used, SPDR can be used as a data storage. This byte is not affected by reset.
10.5.4 Timing Diagram
Figure 10-5 illustrates the clock/data timing.
SCK
SDO DORD = 0
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
SDI DORD = 0
MSB
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
SDO DORD = 1
LSB
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
MSB
SDI DORD = 1
LSB
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
MSB
DATA SAMPLE
Figure 10-5. Clock/Data Timing
MC68HC05L25 Data Sheet, Rev. 3.1 96 Freescale Semiconductor
Register Description
10.5.5 Stop/Wait Condition
The following paragraphs describe stop and wait modes.
10.5.6 Stop Mode
The SPI configured as master mode is not operational during stop mode since the system clock and SPI clock generator are halted. If stop mode occurs while SPI is in progress (transmitting/receiving) and in master mode, the access will halt and remains halted until stop is released. Due to the static architecture, the previous conditions of SCK and SDIO are preserved during stop mode. In slave mode, all accesses are possible during stop mode. However, at the end of transmission, interrupt occurs but the SPI will not be set immediately until after the system clock starts operating. (This operation is transparent to the programmer.)
10.5.7 Wait Mode
In wait mode, the CPU halts but will not affect the SPI operation. Therefore, SPI interrupt in master and slave modes can be executed to wake up the CPU.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 97
Serial Peripheral Interface
MC68HC05L25 Data Sheet, Rev. 3.1 98 Freescale Semiconductor
Chapter 11 LCD Driver
11.1 Introduction
The MC68HC05L25 has 25 or 24 frontplane (FP) and three or four backplane (BP) drivers. The number of drivers for the FP and BP can be selected by software option. The maximum number of segments configurable is either 24 x 4 = 96 or 25 x 3 = 75 segments. The MC68HC05L25 uses a 1/3 biasing method. The bias voltages are supplied from an external source using the VLCD pin. Voltages VLCD1, VLCD2, and VLCD3 are generated internally with resistor divider. There are 11 bytes of data latch for selection (turned on) or nonselection (turned off) of segments. Each byte consists of two FP drivers and either three or four BP drivers depending on the duty configured. The data latch is available in memory locations $21 through $2D and can be accessed by the CPU using the conventional memory access method (LOAD, STORE, BIT operations, etc.). The clock which forms the LCD FP and BP waveforms is supplied by the time base module.
11.2 Block Diagram
Figure 11-1 illustrates the block diagram of the LCD module.
FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP5 FP6 FP7 FP8 FP9
LCD FRONTPLANE DRIVER + DATA LATCH PB7/FP17 PB6/FP18 PB5/FP19
PORTB 1/3 1/4 BACKPLANE
FP4 FP3 FP2 FP1 BP3/FP0 BP2 BP1 BP0 VLCD
LCDE (LCDC)
DRIVER
STATE CONTROL
1/3 1/4
PB4/FP20 PB3/FP21 PB2/FP22 PB1/FP23 PB0/FP24
Figure 11-1. LCD Block Diagram
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 99
LCD Driver
11.3 Functional Description
The following paragraphs provide a functional description of the LCD driver. See Figure 11-15 for a simplified schematic of the LCD system.
11.3.1 LCD Control Register
Address: Read: Write: Reset: $0020 Bit 7 LCDE 0 6 PBEH 0 5 DUTY 0 4 PBEL 0 3 0 0 2 0 0 1 FC 0 Bit 0 LC 0
= Unimplemented
Figure 11-2. LCD Control Register LCDE -- LCD Enable Setting this bit enables the LCD waveforms to appear on the pins. Reset clears this bit. 1 = LCD drivers are operational. Each FP and BP driver outputs the driver waveform specified by the data latch. 0 = LCD drivers are halted. All FP and BP drivers have the same electric potential as VDD. RLCDs are disconnected to reduce DC current. PBEH -- Port B Enable High Nibble This bit enables the port B I/O bits 4-7 that are multiplexed with frontplane drivers 20-17. Reset clears this bit. 0 = PB4-PB7/FP20-FP17 pins function as port B bits 4-7. 0 = PB4-PB7/FP20-FP17 pins function as LCD frontplane drivers 20-17. DUTY -- Duty Cycle Select This bit selects the duty cycle of the LCD waveforms between 1/3 duty and 1/4 duty and selects either BP3 or FP0 for the muxed pin. Reset clears this bit. 1 = 1/3 duty cycle is selected and BP3/FP0 pin functions as FP0. 0 = 1/4 duty cycle is selected and BP3/FP0 pin functions as BP3. PBEL -- Port B Enable Low Nibble This bit enables the port B I/O bits 0-3 that are multiplexed with frontplane drivers 24-21. Reset clears this bit. 1 = PB0-PB3/FP24-FP21 pins function as port B bits 0-3. 0 = PB0-PB3/FP24-FP21 pins function as LCD frontplane drivers 24-21. Bits 3 and 2 -- Reserved These bits are unused and always read as zero. FC and LC -- Fast Charge and Low Current These bits are used to select various values of resistors in the voltage generator resistor chain. Reset clears these bits.
MC68HC05L25 Data Sheet, Rev. 3.1 100 Freescale Semiconductor
Functional Description
Table 11-1. RLCD Configuration
FC X 0 1 LC 0 1 1 Action Default value of approximately 160 k per resistor Resistor value of approximately 860 k per resistor Fast-Charge: For a period of LCDCLK/128 in each frame, the resistor values are reduced to default (value for LC = 0).
11.3.2 Fast Change Option
The RLCD is approximately 160 k at VDD = 3 V by default. This value can be inappropriate for some applications. For those applications that require less DC current drain through the RLCD chain, it may be increased to approximately 860 k at VDD = 3 V by setting the LC bit in LCDCR. Some applications may require the default resistance to drive the capacitive load of the LCD panel, yet do not wish to have the DC current drain of it while the LCD segments are not switching. For a compromise, a fast-charge option is available. The RLCD values are reduced to the default resistance for a fraction of the LCD segment cycle before the LCD segments change, and then are set to low-current mode for the remainder of the LCD cycle frame. The DC current increase is very negligible and will be within a few percent increase of the low-current mode.
BP0
FC CLOCK
Figure 11-3. BP0/FC Clock Timing
11.3.3 LCD Data Registers
The LCD data latches LDAT1 through LDAT11 maintain the ON/OFF data for the FP and BP segments of the LCD. Four bits of data latch are assigned to each frontplane driver from address space $21 through $2D as shown in Figure 11-4. When a logic 1 is written to the bits in the data latch, the applicable FP-BP segment turns ON. When a logic 0 is written to the bits, the segment is turned OFF. The values in the data latches are not initialized and are unknown on reset. If 1/3 duty is selected, each BP3 bit in the data latches is ignored.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 101
LCD Driver Addr Hex $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D Bit Number Sequence Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: LCDE F1B3 F3B3 F5B3 F7B3 F9B3 F11B3 F13B3 F15B3 F17B3 F19B3 F21B3 F23B3 0 6 PBEH F1B2 F3B2 F5B2 F7B2 F9B2 F11B2 F13B2 F15B2 F17B2 F19B2 F21B2 F23B2 0 5 DUTY F1B1 F3B1 F5B1 F7B1 F9B1 F11B1 F13B1 F15B1 F17B1 F19B1 F21B1 F23B1 0 4 PBEL F1B0 F3B0 F5B0 F7B0 F9B0 F11B0 F13B0 F15B0 F17B0 F19B0 F21B0 F23B0 0 3 0 2 0 1 FC F0B1 F2B1 F4B1 F6B1 F8B1 F10B1 F12B1 F14B1 F16B1 F18B1 F20B1 F22B1 F24B1 Bit 0 LC F0B0 F2B0 F4B0 F6B0 F8B0 F10B0 F12B0 F14B0 F16B0 F18B0 F20B0 F22B0 F24B0
Register Name LCD Control Register (LCDCR) LCD Data Register (LDAT1) LCD Data Register (LDAT2) LCD Data Register (LDAT3) LCD Data Register (LDAT4) LCD Data Register (LDAT5) LCD Data Register (LDAT6) LCD Data Register (LDAT7) LCD Data Register (LDAT8) LCD Data Register (LDAT9) LCD Data Register (LDAT10) LCD Data Register (LDAT11) LCD Data Register (LDAT12) LCD Data Register (LDAT13)
F0B3 F2B3 F4B3 F6B3 F8B3 F10B3 F12B3 F14B3 F16B3 F18B3 F20B3 F22B3 F24B3
F0B2 F2B2 F4B2 F6B2 F8B2 F10B2 F12B2 F14B2 F16B2 F18B2 F20B2 F22B2 F24B2
= Unimplemented
Figure 11-4. LCD Data Registers (LDAT1-LDAT13)
11.4 Terminal Description
A total of 27 pins is dedicated to the LCD driver.
11.4.1 VLCD Bias Inputs
VLCD1 through VLCD3 are internal bias voltages for the LCD driver waveforms. VLCD3 potential is available externally as the VLCD pin, and a variable resistor for contrast can be placed between VLCD and VSS. See Figure 11-15.
MC68HC05L25 Data Sheet, Rev. 3.1 102 Freescale Semiconductor
Terminal Description
The LCD uses the three bias voltages typically as follows: 1. VLCD1 = VDD -- 1/3 VLCDA (VLCDA is the ON voltage for the LCD modules.) 2. VLCD2 = VDD -- 2/3 VLCDA (Usually, VLCDA VDD is used.) 3. VLCD3 = VDD -- VLCDA = VLCD (VLCD is the external pin.) The three voltages shown above are arranged so that the external voltages will have a VLCD1 > VLCD2 > VLCD3 relationship in a voltage divider configuration.
11.4.2 Backplane Drivers (BP0-BP3)
Pins BP0-BP3 are the output terminals for the backplane drivers. These are connected to the backplane of the LCD panel. Depending on the duty, the waveforms in Figure 11-5 and Figure 11-6 appear on the backplane pins.
11.4.3 Frontplane Drivers
Pins FP0-FP24 are the output terminals for the frontplane drivers. These are connected to the frontplane of the LCD panel. Depending on the content of the data latch, the waveforms in Figure 11-7 and Figure 11-8 appear on the frontplane drivers.
DUTY = 1/3 1FRAME VDD BP0 VLCD1 VLCD2 VLCD3
VDD BP1 VLCD1 VLCD2 VLCD3
VDD BP2 VLCD1 VLCD2 VLCD3 NOTES:
.
1. BP3 is not used. 2. At 1/3 duty, 1FRAME has three times the cycle of LCD waveform base clock.
Figure 11-5. 1/3 Duty LCD Backplane Driver Waveforms
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 103
LCD Driver
DUTY = 1/4
1FRAME VDD
BP0
VLCD1 VLCD2 VLCD3
VDD VLCD1 BP1 VLCD2 VLCD3
VDD BP2 VLCD1 VLCD2 VLCD3
VDD BP3 VLCD1 VLCD2 VLCD3 NOTE: The element which selects or does not select the BP waveforms is as follows.
VDD SELECTED VLCD1 VLCD2 VLCD3
VDD NOT SELECTED VLCD1 VLCD2 VLCD3
Figure 11-6. 1/4 Duty LCD Backplane Driver Waveforms
MC68HC05L25 Data Sheet, Rev. 3.1 104 Freescale Semiconductor
Terminal Description
DUTY = 1/3 DATA LATCH: 1 . . . . ON (SELECTED)
0. . . . OFF (NOT SELECTED)
CONTENT OF FPX DATA LATCH BP2 -- 0 BP1 0 BP0 0
VDD VLCD1 VLCD2 VLCD3 VDD
BP2 -- 0
BP1 0
BP0 1
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 0
BP1 1
BP0 0
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 1
BP1 0
BP0 0
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 0
BP1 1
BP0 1
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 1
BP1 1
BP0 0
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 1
BP1 0
BP0 1
VLCD1 VLCD2 VLCD3 VDD
BP2 -- 1
BP1 1
BP0 1
VLCD1 VLCD2 VLCD3
. Figure 11-7. 1/3 Duty LCD Frontplane Driver Waveforms
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 105
LCD Driver
DUTY = 1/4 ONLY A PORTION IS ILLUSTRATED CONTENTS OF FPX DATA LATCH BP3 0 BP2 0 BP1 0 BP0 0 VDD VLCD1 VLCD2 VLCD3 VDD BP3 0 BP2 0 BP1 0 BP0 1 VLCD1 VLCD2 VLCD3 VDD BP3 0 BP2 1 BP1 1 BP0 0 VLCD1 VLCD2 VLCD3 NOTE: The fundamental elements which select or do not select the frontplane waveforms are as follows.
VDD VLCD1 SELECTED (1) VLCD2 VLCD3
VDD VLCD1 NOT SELECTED (0) VLCD2 VLCD3
Figure 11-8. 1/4 Duty LCD Frontplane Driver Waveforms
MC68HC05L25 Data Sheet, Rev. 3.1 106 Freescale Semiconductor
LCD Connection and LCD Driver Operation
11.5 LCD Connection and LCD Driver Operation
The connection between the MC68HC05L25 and the seven segments of the LCD panel is discussed in the following paragraphs. Figure 11-9 illustrates a 1/3 duty example. Pins BP0, BP1, BP2, FP0, FP1, and FP2 output the waveforms illustrated in Figure 11-10.
FP CONNECTION a BP CONNECTION a
f
g
b
f
g
b
BP0 (a, b CONNECTED)
e d
c
e d
c
BP1 (c, f, g CONNECTED) BP2 (d, e CONNECTED)
FP0 FP1 FP2 (e, f) (a, d, g) (b, c)
The segment assignments for each bit in the data latch are:
-- D G A -- E F --
FP1
-- -- -- -- -- --
FP0
C B
(Unrelated FP)
FP2 (-- means not assigned in this case)
To display a 4 using the assignments above will have the following data written to LDAT1 and LDAT2.
-- 0 1 0 -- 0 1 X
FP1
-- -- -- -- -- X
FP0
1 1
FP2 (Unrelated FP) (X . . . don't care) (--, X . . . are zero in this case)
Figure 11-9. 1/3 Duty Example
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 107
LCD Driver
DUTY = 1/3 1FRAME VDD BP0 VLCD1 VLCD2 VLCD3
VDD BP1 VLCD1 VLCD2 VLCD3
VDD BP2 VLCD1 VLCD2 VLCD3 FP0 WAVEFORM BP2 -- 0 BP1 1 BP0 0 VDD VLCD1 VLCD2 VLCD3 FP1 WAVEFORM BP2 -- 0 BP1 1 BP0 0 VDD VLCD1 VLCD2 VLCD3 FP2 WAVEFORM BP2 -- 0 BP1 1 BP0 1 VDD VLCD1 VLCD2 VLCD3
Figure 11-10. BP0-BP2 and FP0-FP2 Output Waveforms The electric potential waveform for the F segment (between FP0 and BP1) is illustrated in Figure 11-11. As shown, the LCD ON voltage (VLCD) of the AC waveform is attained, so the F segment will turn ON.
VLCD VLCD1 VLCD2 BP1-FP0 0 -VLCD2 -VLCD1 -VLCD
Figure 11-11. F Segment Potential Waveform
MC68HC05L25 Data Sheet, Rev. 3.1 108 Freescale Semiconductor
LCD Connection and LCD Driver Operation
The electric potential waveform for the E segment (between FP0 and BP2) is illustrated in Figure 11-12. This segment is not turned ON.
VLCD VLCD1 VLCD2 BP2-FP0 0 -VLCD2 -VLCD1 -VLCD
Figure 11-12. E Segment Electric Potential Waveform The methods described will determine whether to turn ON or turn OFF the LCD segment. The waveform elements which select or do not select the BP and FP waveforms are shown in Figure 11-13.
FP DATA LATCH -> SELECTED VDD FP VLCD1 VLCD2 VLCD3 BP SELECTED VDD VLCD1 VLCD2 VLCD3 ON +VLCD +2 VLCD/3 +VLCD/3 0 -VLCD/3 -2 VLCD/3 -VLCD NOT SELECTED VDD VLCD1 VLCD2 VLCD3 OFF +VLCD +2 VLCD/3 +VLCD/3 0 -VLCD/3 -2 VLCD/3 -VLCD ON OFF +VLCD +2 VLCD/3 +VLCD/3 0 -VLCD/3 -2VLCD/3 -VLCD +VLCD +2 VLCD/3 +VLCD/3 0 -VLCD/3 -2VLCD/3 -VLCD 1 0 NOT SELECTED VDD VLCD1 VLCD2 VLCD3
Figure 11-13. Waveform Elements
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 109
LCD Driver
11.6 LCD Waveform Base Clock and LCD Cycle Frame
The clock which produces the LCD FP and BP output waveforms, the LCD waveform back clock, is generated from the time base module. The frequency for the LCD waveform base clock can be changed by the time base control register.
11.6.1 Time Base Control Register 1
Address: Read: Write: Reset: $0010 Bit 7 TBCLK 0 6 0 0 5 LCLK 0 4 RMC4 0 3 RMC3 0 2 RMC2 0 1 RMC1 0 Bit 0 RMC0 0
= Unimplemented
Figure 11-14. Time Base Control Register 1 (TBCR1) LCLK -- LCD Clock The LCLK bit selects the clock for the LCD driver. This bit is cleared on reset. When TBCLK = 0: 1 = XOSC divide by 128 is selected for the LCD clock 0 = XOSC divide by 64 is selected for the LCD clock When TBCLK = 1: 1 = OSC divide by 16,384 is selected for the LCD clock 0 = OSC divide by 8192 is selected for the LCD clock Table 11-2. LCD Waveform Base Clock Frequency
TBCR1 TBCLK LCLK 0 0 1 1 0 1 0 1 XOSC / 64 XOSC / 128 OSC / 8192 OSC / 16384 Divide Ratio LCD Waveform Base Clock Frequency (Hz) (fXOSC = 32.768 kHz) OSC = 2.0 MHz 512 256 244 122 OSC = 4.0 MHz 512 256 488 244 OSC = 4.1943 MHz 512 256 512 256
11.6.2 LCD Cycle Frame
The LCD cycle frame with respect to the LCD waveform base clock and duty is
1 ( LCD Cycle Frame ) = -------------------------------------------------------------------------------------------------( LCD Waveform Base Clock ) ( Duty )
For example, given 1/3 duty and 256 Hz waveform base clock.
1( LCD Cycle Frame ) = ----------------1 256 -3 = 11.72 ms
MC68HC05L25 Data Sheet, Rev. 3.1 110 Freescale Semiconductor
Simplified LCD Schematic
11.7 Simplified LCD Schematic
A simplified schematic of the LCD driver is shown in Figure 11-15.
LCD
FP0
FP1
FP24
BP0
BP1
RFP
RFP
RFP
RBP
RBP
BYPASS CAPS
VDD RLCD VLCD1 RLCD VLCD2 VLCD VR RLCD VLCD3
MC68HC05L25 LCD DRIVER, 1/3 DUTY AND 1/3 BIAS
Figure 11-15. Simplified LCD Schematic
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 111
LCD Driver
MC68HC05L25 Data Sheet, Rev. 3.1 112 Freescale Semiconductor
Chapter 12 Analog Subsystem
12.1 Introduction
The MC68HC05L25 includes a 2-channel, multiplexed input, 8-bit, successive approximation analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port A pins PA4 and PA5.
12.2 Analog Section
The following paragraphs describe the operation and performance of analog modules within the analog subsystem.
12.3 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH = VDD supplying the high reference voltage. Applying an input voltage equal to VREFH produces a conversion result of $FF (full scale). Applying an input voltage equal to VSS produces a conversion result of $00. An input voltage greater than VREFH will convert to $FF with no overflow indication. For ratiometric conversions, VREFH should be at the same potential as the supply voltage being used by the analog signal being measured and should be referenced to VSS.
12.3.1 VREFH
The reference supply for the A/D converter is tied to VDD internally. The low reference is tied to the VSS pin internally.
12.3.2 Accuracy and Precision
The 8-bit conversion result is accurate to within 1.5 LSB, including quantization; however, the accuracy of conversions is tested and guaranteed only with external oscillator operation at VDD = 5 V.
12.4 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog (D/A) converter. Control logic drives the D/A and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion cycle. The conversion process is monotonic and has no missing codes.
12.5 Digital Section
The following paragraphs describe the operation and performance of digital modules within the analog subsystem.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 113
Analog Subsystem
12.5.1 Conversion Times
Each input conversion requires 32 PH2 (bus) clock cycles, which must be at a frequency equal to or greater than 1 MHz.
12.5.2 Internal versus External Oscillator
If the MCU PH2 clock frequency is less than 1 MHz (2-MHz external oscillator), the internal RC oscillator (approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is selected by setting the ADRC bit in the ADSC register. When the internal RC oscillator is being used, these limitations apply: 1. Since the internal RC oscillator is running asynchronously with respect to the PH2 clock, the conversion complete bit (CC) in register ADSC must be used to determine when a conversion sequence has been completed. 2. Electrical noise will slightly degrade the accuracy of the A/D converter. The A/D converter is synchronized to read voltages during the quiet period of the clock driving it. Since the internal and external clocks are not synchronized, the A/D converter occasionally will measure an input when the external clock is making a transition. 3. If the PH2 clock is 1 MHz or greater (for example, external oscillator 2 MHz or greater and SYS1-SYS0 = 0-0), the internal RC oscillator must be turned off and the external oscillator used as the conversion clock.
12.5.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of two external analog signals. Port A pins PA4 and PA5 are shared with the inputs to the multiplexer. NOTE Applying analog voltage to an A/D input pin that is not selected (used as a general-purpose digital I/O port) may result in excessive IDD.
12.6 A/D Subsystem Operation during Wait Modes
The A/D subsystem continues normal operation during wait modes. To decrease power consumption during wait, the ADON and ADRC bits in the A/D status and control register should be cleared if the A/D subsystem is not being used.
12.7 A/D Subsystem Operation during Stop Modes
When stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions. Any pending conversion is aborted. When the oscillator resumes operation upon leaving stop mode, a finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its rated accuracy. The delays built into the MC68HC05L25 when coming out of stop mode are sufficient for this purpose. No explicit delays need to be added to the application software.
MC68HC05L25 Data Sheet, Rev. 3.1 114 Freescale Semiconductor
A/D Status and Control Register
12.8 A/D Status and Control Register
The ADSC register reports the completion of A/D conversion and provides control over oscillator selection, analog subsystem power, and input channel selection.
Address: Read: Write: Reset: 0 $001E Bit 7 CC 6 ADRC 0 5 ADON 0 4 0 0 3 0 0 2 CH2 0 1 CH1 0 Bit 0 CH0 0
= Unimplemented
Figure 12-1. A/D Status and Control Register (ADSC) CC -- Conversion Complete This read-only status bit is set when a conversion sequence has completed and data is ready to be read from the ADDR register. CC is cleared when a channel is selected for conversion, when data is read from the ADDR register, or when the A/D subsystem is turned off. Once a conversion has been started, conversions of the selected channel will continue every 32 PH2 clock cycles until the ADSC register is written to again. During continuous conversion operation, the ADDR register will be updated with new data and the CC bit will be set every 32 PH2 clock cycles. Also, data from the previous conversion will be overwritten regardless of the state of the CC bit. 1 = A/D conversion sequence completed 0 = A/D subsystem is off or conversion is in progress ADRC -- RC Oscillator Control When ADRC is set, the A/D subsystem operates from the internal RC oscillator instead of the PH2 clock. The RC oscillator requires a time, tRCON, to stabilize before accurate conversion results can be obtained. See 12.5.2 Internal versus External Oscillator for more information. 1 = RC OSC on 0 = RC OSC off ADON -- A/D Subsystem On When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to stabilize before accurate conversion results can be attained. 1 = A/D subsystem enabled 0 = A/D subsystem disabled Bits 4:3 -- Reserved These bits are not used and always read as zero. CH2:CH0 -- Channel Select Bits Channel select bits CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D converter. Channels 0 and 1 correspond to port A input pins PA4 and PA5. Channels 4-6 are used for reference measurements. In single-chip mode, channels 2, 3, and 7 are reserved. If a conversion is attempted with channel 2, 3, or 7 selected, the result will be undefined. Table 12-1 lists the inputs selected by bits CH0-CH2. If the ADON bit is set, and an input from channel 0 or 1 is selected, the corresponding port A pin will not function as a digital port. If the port A data register is read when DDR = 0 while the A/D is on and one of the shared input channels is selected using bits CH0-CH2, the corresponding port A pin will
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 115
Analog Subsystem
read as a logic 0. If the DDR = 1, the port A data register will read the output latch value. The remaining port A pins will read normally. To digitally read a multiplexed port A pin as an input port, the A/D subsystem must be disabled (ADON = 0) or input channels 2-7 must be selected. Table 12-1. A/D Multiplexer Input Channel Assignments
Channel 0 1 2 3 4 5 6 7 Signal AD0 Port A Bit 4 AD1 Port A Bit 5 Reserved Reserved VREFH = VDD (VREFH + VREFL)/2 VREFL = VSS Factory Test
12.9 A/D Conversion Data Register
This register contains the output of the A/D converter.
Address: Read: Write: Reset: = Unimplemented Unaffected by Reset $001D Bit 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
Figure 12-2. A/D Conversion Value Data Register (ADDR)
MC68HC05L25 Data Sheet, Rev. 3.1 116 Freescale Semiconductor
Chapter 13 Event Counter
13.1 Features
Event counter features include: * Asynchronous Input up to 6 MHz * Overflow Interrupt * Event Count Complete Interrupt * Variable Gate Generation * Spike Filter * Effective 18-Bit Resolution
13.2 Introduction
The event counter consists of a 16-bit counter externally driven from the event counter pin, with input gate generation and filtering circuitry. Average frequency measurements can be made over user specified intervals ranging from 4 to 60 ms (with 2-MHz bus clock). Measurements are continuously repeated at a user specified rate. A maskable and resetable event count complete interrupt and event counter overflow interrupt are available. Using the overflow interrupt, an effective 18-bit count can be achieved. See Table 13-1.
INTERNAL HC05 BUS
8
8
16-BIT COUNTER
FILTER
EVI
EVOE
EVOF
EVCE
SYSTEM CLOCK
1/214
ECCI
EVIE GATE SIGNAL CONTROL
EVOI
EVIF
EVC TIMING REGISTER
Figure 13-1. Event Counter Block Diagram
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 117
Event Counter
13.3 Event Counter Status/Control Register
Address: Read: Write: Reset: $002E Bit 7 EVCE 0 6 EVIE 0 5 EVOE 0 4 EVIF 0 3 EVOF 0 2 0 RCCF 0 1 0 ROIF 0 0 Bit 0 0
= Unimplemented
Figure 13-2. Event Counter Status/Control Register (EVSC) EVCE -- Event Counter Enable 1 = Event counter enabled 0 = Event counter disabled EVIE -- Event Counter Complete Interrupt Enable 1 = Event counter complete interrupt enabled 0 = Event counter complete interrupt disabled EVOE -- Event Counter Overflow Enable 1 = Event counter overflow interrupt enabled 0 = Event counter overflow interrupt disabled EVIF -- Event Counter Complete Interrupt Flag (read only) 1 = Flag set when gate delay time expires 0 = Flag cleared when logic 1 is written to ROIF EVOF -- Event Counter Overflow Flag (read only) 1 = Flag set when gate delay time expires 0 = Flag cleared when logic 1 is written to ROIF RCCF -- Reset Count Complete Interrupt Flag (write only) When a logic 1 is written to this bit, EVIF is cleared. Always reads as zero. ROIF -- Reset Overflow Interrupt Flag (write only) When a logic 1 is written to this bit, EVOF is cleared. Always reads as zero. Bit 0 -- Reserved This bit is not used and always reads as zero.
MC68HC05L25 Data Sheet, Rev. 3.1 118 Freescale Semiconductor
Event Counter Timing Register
13.4 Event Counter Timing Register
Address: Read: Write: Reset: $002F Bit 7 WT3 1 6 WT2 1 5 WT1 1 4 WT0 1 3 MT3 1 2 MT2 1 1 MT1 1 Bit 0 MT0 1
Figure 13-3. Event Counter Timing Register (EVTR) This register controls generation of the gate signal which is used to control the input to the event counter. See Figure 13-5. The value in the event counter timing register determines the length of the measurement and the length of the wait time between measurements. See Table 13-1 and Table 13-2. The measurement time bits, MT3 through MT0, determine the length of time that the input gate on the EVI pin is open. During this time the gate signal is a logic 1. The wait time bits, WT3 through WT0, determine the length of time that the gate signal is a logic 0. tgc is the length of a unit count. The specification for tgc is found in Chapter 15 Electrical Specifications. After being enabled, EVCE = 1, the event counter will make measurements continuously. If the event counter timing register is written, the current measurement will be aborted, and a new measurement will be initiated.
EVI
... MT3:0 X tGC WT3:0 X tGC
GATE SIGNAL
COUNTER INPUT COUNT 1 2 3
... 1 2 3
N-1
N
4
5
Figure 13-4. Event Counter Input Timing Example
The input to the event counter is the logical AND of the signal on the EVI pin and the internally generated gate signal. The rising edges of the counter input signal are used to generate the events that increment the counter. If the pulse width of the ANDed signal is less than that which the circuitry is capable of detecting, the narrow pulse will not be allowed to pass through the filter.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 119
Event Counter
Table 13-1. Measurement Time Nibble
MT3:MT0 $X0 $X1 $X2 $X3 $X4 $X5 $X6 $X7 Measurement Time 0 ms 3.9063 ms 7.8125 ms 11.719 ms 15.625 ms 19.531 ms 23.438 ms 27.344 ms MT3:MT0 $X8 $X9 $XA $XB $XC $XD $XE $XF Measurement Time 31.250 ms 35.156 ms 39.063 ms 42.969 ms 46.875 ms 50.781 ms 54.688 ms 58.593 ms
Table 13-2. Wait Time Nibble
WT3:WT0 $0X ms $1X ms $2X ms $3X ms $4X ms $5X ms $6X ms $7X ms Wait Time 0 ms 3.9063 ms 7.8125 ms 11.719 ms 15.625 ms 19.531 ms 23.438 ms 27.344 ms WT3:WT0 $8x $9x $Ax $BX $CX $DX $EX $FX Wait Time 31.250 ms 35.156 ms 39.063 ms 42.969 ms 46.875 ms 50.781 ms 54.688 ms 58.593 ms
NOTE: SYS0 and SYS1 = 00, fosc = 4.1943 MHz
EVTR WRITE 1 SYSTEM CLOCK 2 3 4 1 2 16,384 16,385
...
DATA & INTERRUPT CLEAR
...
GATE SIGNAL NOTE: MT3 THROUGH MT0 = -$X1
...
Figure 13-5. Event Counter Gate Signal Timing Example
The above example illustrates the relation of the gate signal to external oscillator clocks for the case of MT3-MT0 = $1. The beginning of the gate signal can be caused by a write to the event counter timing register or expiration of the wait time. If the event counter timing register is written, the rising edge of the gate signal will occur
MC68HC05L25 Data Sheet, Rev. 3.1 120 Freescale Semiconductor
Event Counter Interrupts
on the fourth internal processor clock cycle of the write to the event counter timing register. The event counter data registers are cleared on the rising edge of the internal gate signal. The external gate signal rises two clock cycles later. After MT3-MT0 x tgt, the gate signal will rise, terminating the measurement time. The gate signal will be the same length for all successive measurements. Unless the start of the gate delay signal and the event counter input signal are externally synchronized, the value of the least significant bit of the event counter data low register may arbitrarily change. If the fast oscillator, OSC, is disabled, the event counter will not function properly.
13.5 Event Counter Interrupts
The event counter complete interrupt (ECCI) is generated at the falling edge of the gate signal. This interrupt indicates the presence of valid data in the event counter data registers. Since reading the data registers during the measurement time may give invalid results, the CPU must read the data registers before the rising edge of the gate signal. The event counter complete interrupt can be cleared by writing a one to RCCF. The event counter complete interrupt is cleared automatically at the beginning of each measurement. The event counter overflow interrupt (EVOF) is generated if the count exceeds 65,535, the maximum value of the 16-bit event counter. This interrupt can be used to indicate an invalid measurement or to increase the resolution of the event counter, which will be described later. The event counter overflow interrupt can be cleared by writing a one to ROIF. The event counter overflow interrupt is cleared automatically at the beginning of each measurement. If an overflow occurs (the counter increments beyond $FFFF), the event counter overflow flag (EVOF) will be set. If EVOE is set, an interrupt will be generated. Following an overflow, the event counter will increment from zero. The resolution of the event counter can be increased by using the event counter overflow interrupt. If it is a count of more than 65,535 the maximum value of the 16-bit event counter is encountered, the event counter overflow interrupt service routine should note the number of "roll-overs" that occur. The overflow interrupt service routine should not clear the event counter interrupt. In this way, the user can be assured that the correct count has been recorded.
13.6 Event Counter During Wait Mode
The event counter continues to operate in wait mode. If EVOE is set and an event counter overflow interrupt occurs, the processor will exit wait mode. If EVIE is set and an event counter interrupt occurs, the processor will exit wait mode.
13.7 Event Counter During Stop Mode
In stop mode, the event counter is disabled.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 121
Event Counter
13.8 Event Counter Data Registers
Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented $0030 Bit 7 BIT15 6 BIT14 5 BIT13 4 BIT12 3 BIT11 2 BIT10 1 BIT9 Bit 0 BIT8
Figure 13-6. Event Counter Data High Register (EVDH)
Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented $0031 Bit 7 BIT7 6 BIT6 5 BIT5 4 BIT4 3 BIT3 2 BIT2 1 BIT1 Bit 0 BIT0
Figure 13-7. Event Counter Data Low Register (EVDL) These read-only registers are the basis of all event counter operations. While the gate signal is low, the value of the most recent event count will remain in the event counter data registers. After the event counter interrupt, the result of the event count can be read. If the event counter data registers are read while the gate signal is high, an incorrect value may result.
MC68HC05L25 Data Sheet, Rev. 3.1 122 Freescale Semiconductor
Chapter 14 Instruction Set
14.1 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
14.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * Inherent * Immediate * Direct * Extended * Indexed, no offset * Indexed, 8-bit offset * Indexed, 16-bit offset * Relative
14.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
14.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
14.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 123
Instruction Set
14.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
14.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
14.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
14.2.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Freescale assembler determines the shortest form of indexed addressing.
14.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
MC68HC05L25 Data Sheet, Rev. 3.1 124 Freescale Semiconductor
Instruction Types
14.3 Instruction Types
The MCU instructions fall into these five categories: * Register/memory instructions * Read-modify-write instructions * Jump/branch instructions * Bit manipulation instructions * Control instructions
14.3.1 Register/Memory Instructions
These instructions operate on central processor unit (CPU) registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 14-1. Register/Memory Instructions
Instruction Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 125
Instruction Set
14.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE Do not use read-modify-write operations on write-only registers. Table 14-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
MC68HC05L25 Data Sheet, Rev. 3.1 126 Freescale Semiconductor
Instruction Types
14.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 14-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 127
Instruction Set
14.3.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 14-4. Bit Manipulation Instructions
Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Mnemonic BCLR BRCLR BRSET BSET
14.3.5 Control Instructions
These instructions act on CPU registers and control CPU operation during program execution. Table 14-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT
MC68HC05L25 Data Sheet, Rev. 3.1 128 Freescale Semiconductor
Instruction Set Summary
14.4 Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 1 of 6)
Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
2 A9 ii B9 dd 3 C9 hh ll 4 D9 ee ff 5 4 E9 ff 3 F9 2 AB ii BB dd 3 CB hh ll 4 DB ee ff 5 4 EB ff 3 FB 2 A4 ii B4 dd 3 C4 hh ll 4 D4 ee ff 5 4 E4 ff 3 F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 2F 2E dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ---------- ---------- ----------
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 129
Cycles
Effect on CCR
Operand
Address Mode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 2 of 6)
Opcode Source Form
BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Description
H I NZC
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
2 A5 ii B5 dd 3 C5 hh ll 4 D5 ee ff 5 4 E5 ff 3 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
--------
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
----------
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
--------
BSET n opr
Set Bit n
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC05L25 Data Sheet, Rev. 3.1 130 Freescale Semiconductor
Cycles
6 2 2
Effect on CCR
Operand
Address Mode
Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 3 of 6)
Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
Compare Accumulator with Memory Byte
(A) - (M)
----
2 A1 ii B1 dd 3 C1 hh ll 4 D1 ee ff 5 4 E1 ff 3 F1 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
2 A3 ii B3 dd 3 C3 hh ll 4 D3 ee ff 5 4 E3 ff 3 F3 3A 4A 5A 6A 7A dd 5 3 3 6 5
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
2 A8 ii B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff 3 F8 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 BD dd 5 CD hh ll 6 DD ee ff 7 6 ED ff 5 FD
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
----------
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 131
Cycles
5 3 3 6 5
Effect on CCR
Operand
Address Mode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 4 of 6)
Opcode Source Form
LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Load Accumulator with Memory Byte
A (M)
----
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH
2 A6 ii B6 dd 3 C6 hh ll 4 D6 ee ff 5 4 E6 ff 3 F6 2 AE ii BE dd 3 CE hh ll 4 DE ee ff 5 4 EE ff 3 FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 36 46 56 66 76 9C ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 1 1 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
Rotate Byte Left through Carry Bit
C b7 b0
----
ff dd
Rotate Byte Right through Carry Bit
b7 b0
C
----
ff
Reset Stack Pointer
SP $00FF
----------
MC68HC05L25 Data Sheet, Rev. 3.1 132 Freescale Semiconductor
Cycles
Effect on CCR
Operand
Address Mode
Instruction Set Summary
Table 14-6. Instruction Set Summary (Sheet 5 of 6)
Opcode Source Form Operation Description
SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ----------
H I NZC
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
2 A2 ii B2 dd 3 C2 hh ll 4 D2 ee ff 5 4 E2 ff 3 F2 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
----
--
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
Subtract Memory Byte from Accumulator
A (A) - (M)
----
2 A0 ii B0 dd 3 C0 hh ll 4 D0 ee ff 5 4 E0 ff 3 F0
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
TAX TST opr TSTA TSTX TST opr,X TST ,X
Transfer Accumulator to Index Register
INH DIR INH INH IX1 IX
97 3D 4D 5D 6D 7D dd
Test Memory Byte for Negative or Zero
(M) - $00
----
--
ff
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 133
Cycles
9 6 1 0 2 4 3 3 5 4
Effect on CCR
Operand
Address Mode
Instruction Set
Table 14-6. Instruction Set Summary (Sheet 6 of 6)
Opcode Source Form
TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operation
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
Description
A (X)
H I NZC
---------- -- 0 ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
INH INH
9F 8F
Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
14.5 Opcode Map
See Table 14-7.
MC68HC05L25 Data Sheet, Rev. 3.1 134 Freescale Semiconductor
Cycles
2 2
Effect on CCR
Operand
Address Mode
Freescale Semiconductor MC68HC05L25 Data Sheet, Rev. 3.1 135
Table 14-7. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2
DIR 3
Read-Modify-Write INH INH IX1 4 5 6
IX 7
Control INH INH 8
9 RTI INH 6 RTS INH
IMM A
2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2
DIR B
Register/Memory EXT IX2 C
4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3
IX1 E
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
IX F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB
0
1
9
D
5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
0 1 2 3 4 5 6 7 8 9 A B C D E F
5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1
2 2 2
10 SWI INH
2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2
2 STOP INH 2 2 WAIT TXA INH 1 INH
6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB
3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3
0 1 2 3 4 5 6 7 8 9 A B C D E F
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
Opcode Map
LSB of Opcode in Hexadecimal
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
Instruction Set
MC68HC05L25 Data Sheet, Rev. 3.1 136 Freescale Semiconductor
Chapter 15 Electrical Specifications
15.1 Introduction
This section contains electrical specifications for the MC68HC05L25.
15.2 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply Voltage Input Voltage (Normal Digital Level) Current Drain Per Pin Excluding VDD and VSS Storage Temperature Range NOTE: Voltages referenced to VSS Symbol VDD VIN I TSTG Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 25 -65 to +150 Unit V V mA C
NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 15.6 DC Electrical Characteristics (VDD = 3.3 V) and 15.7 DC Electrical Characteristics (VDD = 5.0 V) for guaranteed operating conditions.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 137
Electrical Specifications
15.3 Operating Range
Characteristic Operating Temperature Range MC68HC05L25 (Standard) Symbol TA Value TL to TH 0 to +70 Unit C
15.4 Thermal Characteristics
Characteristic Thermal Resistance MC68HC05L25FA (48-pin VQFP) MC68HC05L25PB (52-pin TQFP) Symbol JA Value 195 126 Unit C/W
15.5 DC Operating Characteristics
Characteristic Operating Voltage Internal Operating Frequency fOP = 1.0 MHz Internal Operating Frequency fOP = 2.1 MHz NOTE: VSS = 0 Vdc, TA = 0 C to +7 0C, unless otherwise noted Symbol Min Max Unit
VDD
3.0 4.5
5.5 5.5
V
MC68HC05L25 Data Sheet, Rev. 3.1 138 Freescale Semiconductor
DC Electrical Characteristics (VDD = 3.3 V)
15.6 DC Electrical Characteristics (VDD = 3.3 V)
Characteristic Output Voltage ILoad = 10.0 A Output High Voltage (ILoad = -0.4 mA) PA4:PA7, PB0:PB7, and PC0:PC1 Output Low Voltage (ILoad = 0.8 mA) PA0:PA7, PB0:PB7, and PC0:PC3 (ILoad = 20 mA) PA0:PA3 Input High Voltage PA0:PA7, PB0:PB7, and PC0:PC3, IRQ, RESET, and XOSC1 Input Low Voltage PA0:PA7, PB0:PB7, and PC0:PC3, IRQ, RESET, and XOSC1 Supply Current (See Notes) Run (fOP = 1.0 MHz) Wait (fOP = 1.0 MHz) Stop With Time Base Running; LCD Off With All Clocks Halted I/O Ports Hi-Z Leakage Current (Without Individual Pullup Activated) PA0:PA7, PB0:PB7, and PC0:PC3 Pullup Current (With Individual Pullup Activated) PA0:PA7 and PB0:PB7 PC0:PC3 Input Current RESET, IRQ, and XOSC1 Capacitance Ports (As Input or Output) RESET, IRQ Crystal Oscillator Mode Feedback Resistor OSC1 to OSC2 XOSC1 to XOSC2 Crystal Oscillator Mode Damping Resistor on XOSC2 RESET Pin Pullup Resistance
NOTES:
Symbol VOL VOH VOH
Min -- VDD -0.1 VDD -0.8
Typ -- -- --
Max 0.1 -- --
Unit V V
VOL
-- -- 0.7 x VDD
-- -- --
0.4 1.0 VDD
V
VIH
V
VIL
VSS
--
0.3 x VDD
V
IDD
-- -- -- --
1.5 1.0 8.0 2.0 --
8.0 5.0 20 10 10
mA mA A A A
IIL
--
IIL IIN COUT CIN ROF RXOF RXOD RRST
6 20 --
20 60 --
60 180 1
A A
-- -- 1 2.7 160 20
-- -- 2 5.5 320 60
12 8 3 8.2 480 120
pF
M k k
1. 2. 3. 4. 5. 6. 7.
VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only Wait IDD: Only time base active Run (Operating) IDD, wait IDD: Measured using external square wave clock source to OSC1 (fOP = 1.0 MHz); all inputs 0.2 Vdc from rail; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 Wait and stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc Wait and stop IDD are affected linearly by the OSC2, XOSC2 capacitance.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 139
Electrical Specifications
15.7 DC Electrical Characteristics (VDD = 5.0 V)
Characteristic Output Voltage ILoad = 10.0 A Output High Voltage (ILoad = -0.8 mA) PA4:PA7, PB0:PB7, and PC0:PC1 Output Low Voltage (ILoad = 0.8 mA) PA0:PA7, PB0:PB7, and PC0:PC3 (ILoad = 20 mA) PA0:PA3 Input High Voltage PA0:PA7, PB0:PB7, and PC0:PC3, IRQ, RESET, and XOSC1 Input Low Voltage PA0:PA7, PB0:PB7, and PC0:PC3, IRQ, RESET, and XOSC1 Supply Current (See Notes) Run (fOP = 2.1 MHz) Wait (fOP = 2.1 MHz) Stop With Time Base Running; LCD Off With All Clocks Halted I/O Ports Hi-Z Leakage Current (Without Individual Pullup Activated) PA0:PA7, PB0:PB7, and PC0:PC3 Pullup Current (With Individual Pullup Activated) PA0:PA7 and PB0:PB7 PC0:PC3 Input Current RESET, IRQ, and XOSC1 Capacitance Ports (As Input or Output) RESET, IRQ Crystal Oscillator Mode Feedback Resistor OSC1 to OSC2 XOSC1 to XOSC2 Crystal Oscillator Mode Damping Resistor on XOSC2 RESET Pin Pullup Resistance
NOTES:
Symbol VOL VOH VOH
Min -- VDD -0.1 VDD -0.8
Typ -- -- --
Max 0.1 -- --
Unit V V
VOL
-- -- 0.7 x VDD
-- -- --
0.4 0.8 VDD
V
VIH
V
VIL
VSS
--
0.3 x VDD
V
IDD
-- -- -- --
3.0 2.0 17 3.0 --
12 6.0 40 15 10
mA mA A A A
IIL
--
IIH IIN COUT CIN ROF RXOF RXOD RRST
10 20 --
30 60 --
90 180 1
A A
-- -- 1 2.7 160 10
-- -- 2 5.5 320 32
12 8 3 8.2 480 70
pF
M k k
1. 2. 3. 4. 5. 6. 7.
VDD = 5.0 Vdc 0.5 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted All values shown reflect average measurements. Typical values at midpoint of voltage range, 25 C only Wait IDD: Only time base active Run (Operating) IDD, wait IDD: Measured using external square wave clock source to OSC1 (fOP = 2.1 MHz); all inputs 0.2 Vdc from rail; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 Wait, stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc Wait, stop IDD is affected linearly by the OSC2, XOSC2 capacitance.
MC68HC05L25 Data Sheet, Rev. 3.1 140 Freescale Semiconductor
LCD DC Electrical Characteristics (VDD = 3.0 V, VLCD = 0 V)
15.8 LCD DC Electrical Characteristics (VDD = 3.0 V, VLCD = 0 V)
Characteristic LCD Bias Resistance Default Low-Current Mode Output Current, Backplanes and Frontplanes High-Current State (Default) VO = 2.85 V VO = 1.85 V VO = 1.15 V VO = 0.15 V Output Current, Backplanes and Frontplanes Low-Current State VO = 2.85 V VO = 1.85 V VO = 1.15 V VO = 0.15 V Symbol RLCD Min 80 430 Typ 160 860 Max 240 1300 Unit k
IBH
-400 -10 1 20
-260 -2.8 4 50
-120 -1 10 80
A
IBL
-400 -1 0.1 20
-260 -0.2 0.6 50
-120 -0.05 1 80
A
NOTES: 1. All values shown reflect average measurements. These values are design targets and not characterization results. 2. If the FC option is selected, for time 1/(32 x fLCD) after the backplane or frontplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitors to charge quickly. Then the circuit is returned to the low-current state until the next voltage level change occurs.
15.9 LCD DC Electrical Characteristics (VDD = 5.0 V, VLCD = 2.0 V)
Characteristic LCD Bias Resistance Default Low-Current Mode Output Current, Backplanes and Frontplanes High-Current State (Default) VO = 4.85 V VO = 3.85 V VO = 3.15 V VO = 2.15 V Output Current, Backplanes and Frontplanes Low-Current State VO = 4.85 V VO = 3.85 V VO = 3.15 V VO = 2.15 V Symbol RLCD Min 80 430 Typ 160 860 Max 240 1300 Unit k
IBH
-660 -10 1 20
-440 -3.8 4.2 50
-220 -1 10 80
A
IBL
-660 -1 0.2 20
-440 -0.2 1.2 50
-220 -0.05 3 30
A
NOTES: 1. All values shown reflect average measurements. These values are design targets and not characterization results. 2. If the FC option is selected, for time 1/(32 x fLCD) after the backplane or frontplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitors to charge quickly. Then the circuit is returned to the low-current state until the next voltage level change occurs.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 141
Electrical Specifications
15.10 A/D Converter Characteristics
Characteristic Resolution Absolute Accuracy VDD = 4.5 to 5.5 V VDD = 3.0 to 3.6 V Conversion Range ADC On Current Stabilization TIme RC Oscillator Stabilization Time Conversion Time (Includes Sampling Time) External Clock (MCU System Clock) Internal RC Oscillator (ADRC = 1) Monotonicity Zero Input Reading Ratiometric Reading Sample Acquisition Time External Clock (MCU System Clock) Internal RC Oscillator (ADRC = 1) Input Capacitance Analog Input Voltage Input Leakage AD0 and AD1 Symbol -- -- -- tADON tRCON -- -- -- -- 00 FF 01 FF -- -- VSS -- -- 32 -- Min 8 1.5 3 VDD 100 5 32 32 Max Units Bit LSB LSB V s s tAD s Hex Hex tAD = tcyc if clock source equals MCU. Error includes quantization. Comments
Inherent Within Total Error VIN = 0 V VIN = VDD Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. tAD = tcyc if clock source equals MCU.
--
12 -- -- VSS
12 12 8 VDD
tAD s pF V
-- --
--
--
400
nA
The external system error caused by input leakage current is approximately equal to the product of R source and input current.
NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted
MC68HC05L25 Data Sheet, Rev. 3.1 142 Freescale Semiconductor
Control Timing (VDD = 3.3 V)
15.11 Control Timing (VDD = 3.3 V)
Characteristic Frequency of Operation OSC Crystal Oscillator Option XOSC Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (fosc / 2) External Clock (fosc / 2) Cycle Time (1 / fOP) Crystal Oscillator Startup Time (Crystal Oscillator Option) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period OSC1 Pulse Width Event Counter Gate Count Symbol fOSC fXOSC fOSC fOP tCYC tOXON tRL tILIH tILIL t tGC Min -- -- dc -- dc 1 000 -- 1.5 250 Note 2 200 16,384 Typ -- 32.768 -- -- -- -- -- -- -- -- -- 16,384 Max 2.0 -- 2.0 1.0 1.0 -- 100 -- -- -- -- 16,384 Unit MHz kHz MHz MHz ns ms tCYC ns tCYC ns fOSC
NOTES: 1. VDD = 3.3 Vdc 0.3 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
15.12 Control Timing (VDD = 5.0 V)
Characteristic Frequency of Operation OSC Crystal Oscillator Option XOSC Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (fosc / 2) External Clock (fosc / 2) Cycle Time (1 / fOP) Crystal Oscillator Startup Time (Crystal Oscillator Option) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period OSC1 Pulse Width Event Counter Gate Count Symbol fOSC fXOSC fOSC fOP tCYC tOXON tRL tILIH tILIL t tGC Min -- -- dc -- dc 480 -- 1.5 125 Note 2 90 16,384 Typ -- 32.768 -- -- -- -- -- -- -- -- -- 16,384 Max 4.2 -- 4.2 2.1 2.1 -- 100 -- -- -- -- 16,384 Unit MHz kHz MHz MHz ns ms tCYC ns tCYC ns fOSC
NOTES: 1. VDD = 5.0 Vdc 0.5 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 143
Electrical Specifications
MC68HC05L25 Data Sheet, Rev. 3.1 144 Freescale Semiconductor
Chapter 16 Mechanical Specifications
The MC68HC05L25 is available in the following packages: * 48-pin quad flat pack (VQFP) * 52-pin thin quad flat pack (TQFP) Package specifications for the MC68HC05L25 were not available at the time of this publication. Contact your local Freescale sales office for the latest information.
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 145
Mechanical Specifications
MC68HC05L25 Data Sheet, Rev. 3.1 146 Freescale Semiconductor
Chapter 17 Ordering Information
17.1 Introduction
This section contains instructions for ordering custom-masked ROM MCUs.
17.2 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Freescale representative. Submit the following items when ordering MCUs: * A current MCU ordering form that is completely filled out (Contact your Freescale sales office for assistance.) * A copy of the customer specification if the customer specification deviates from the Freescale specification for the MCU * Customer's application program on one of the media listed in 17.3 Application Program Media
17.3 Application Program Media
Please deliver the application program to Freescale in one of the following media: * Macintosh(R)(1) 3 1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M) * MS-DOS(R)(2) or PC-DOSTM(3) 3 1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M) * MS-DOS(R) or PC-DOSTM 5 1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information: * Customer name * Customer part number * Project or product name * File name of object code * Date * Name of operating system that formatted diskette * Formatted capacity of diskette
1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 147
Ordering Information
On diskettes, the application program must be in Freescale's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. NOTE Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all non-user ROM locations blank. Refer to the current MCU ordering form for additional requirements. Freescale may request pattern re-submission if non-user areas contain any non-zero code. If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. In addition to the object code, a file containing the source code can be included. Freescale keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code.
17.4 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Freescale inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain non-user ROM code, such as self-check code. Freescale sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Freescale will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Freescale. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask.
17.5 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Freescale manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Freescale then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Freescale Quality Assurance.
MC68HC05L25 Data Sheet, Rev. 3.1 148 Freescale Semiconductor
MC Order Numbers
17.6 MC Order Numbers
The following table shows the MC order numbers for the available package types.
MC Order Number MC68HC05L25FA MC68HC05L25PB NOTES: FA = 48-pin quad flat pack (VQFP) PB = 52-pin thin quad flat pack (TQFP) Operating Temperature Range -0 to 70C -0 to 70C
MC68HC05L25 Data Sheet, Rev. 3.1 Freescale Semiconductor 149
Ordering Information
MC68HC05L25 Data Sheet, Rev. 3.1 150 Freescale Semiconductor
blank
How to Reach Us:
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved.
MC68HC05L25 Rev. 3.1, 9/2005

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